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dialect: (riscv_snitch) prettify frep custom syntax CI - MLIR-based Testing #6755: Pull request #1791 synchronize by superlopuh
November 16, 2023 10:37 3m 9s sasha/riscv/frep-custom-format
sasha/riscv/frep-custom-format
November 16, 2023 10:37 3m 9s
core: Allow multiple inheritance when one parent is generic (#1794) CI - MLIR-based Testing #6754: Commit 4fd9a3a pushed by compor
November 16, 2023 09:37 3m 4s main
main
November 16, 2023 09:37 3m 4s
dialects: (riscv) add double-precision fmadd and fmsub (#1790) CI - MLIR-based Testing #6753: Commit 4b87e5b pushed by compor
November 16, 2023 08:38 3m 12s main
main
November 16, 2023 08:38 3m 12s
backend: (riscv) Exclude FP registers from RISC-V regalloc in the pre… CI - MLIR-based Testing #6752: Commit e041198 pushed by compor
November 16, 2023 08:35 3m 4s main
main
November 16, 2023 08:35 3m 4s
pip dev(deps-dev): bump wgpu from 0.11.0 to 0.12.0 (#1795) CI - MLIR-based Testing #6751: Commit 3500600 pushed by math-fehr
November 16, 2023 02:57 3m 11s main
main
November 16, 2023 02:57 3m 11s
pip prod(deps): bump pyright from 1.1.335 to 1.1.336 CI - MLIR-based Testing #6750: Pull request #1796 opened by dependabot bot
November 16, 2023 02:53 3m 4s dependabot/pip/pyright-1.1.336
dependabot/pip/pyright-1.1.336
November 16, 2023 02:53 3m 4s
pip dev(deps-dev): bump wgpu from 0.11.0 to 0.12.0 CI - MLIR-based Testing #6749: Pull request #1795 opened by dependabot bot
November 16, 2023 02:52 3m 9s dependabot/pip/wgpu-0.12.0
dependabot/pip/wgpu-0.12.0
November 16, 2023 02:52 3m 9s
core: Allow multiple inheritance when one parent is generic CI - MLIR-based Testing #6748: Pull request #1794 opened by math-fehr
November 16, 2023 01:26 3m 15s fehr/multiple-inheritance-irdl
fehr/multiple-inheritance-irdl
November 16, 2023 01:26 3m 15s
interactive: condense feature added and condense_pass list calculated dynamically! (3/7) CI - MLIR-based Testing #6747: Pull request #1793 synchronize by dshaaban01
November 15, 2023 21:17 3m 3s dalia/condense.2
dalia/condense.2
November 15, 2023 21:17 3m 3s
interactive: condense feature added and condense_pass list calculated dynamically! (3/7) CI - MLIR-based Testing #6746: Pull request #1793 opened by dshaaban01
November 15, 2023 21:06 4m 40s dalia/condense.2
dalia/condense.2
November 15, 2023 21:06 4m 40s
dialects: (riscv_snitch) add FrepYieldOp to dialect definition CI - MLIR-based Testing #6745: Pull request #1792 opened by superlopuh
November 15, 2023 20:57 3m 5s sasha/riscv/frep-yield
sasha/riscv/frep-yield
November 15, 2023 20:57 3m 5s
dialect: (riscv_snitch) prettify frep custom syntax CI - MLIR-based Testing #6744: Pull request #1791 opened by superlopuh
November 15, 2023 20:35 3m 23s sasha/riscv/frep-custom-format
sasha/riscv/frep-custom-format
November 15, 2023 20:35 3m 23s
misc: (Makefile) Use a better message for tests target (#1787) CI - MLIR-based Testing #6743: Commit fb162bb pushed by compor
November 15, 2023 16:35 3m 11s main
main
November 15, 2023 16:35 3m 11s
dialects: (riscv) add double-precision fmadd and fmsub CI - MLIR-based Testing #6742: Pull request #1790 opened by superlopuh
November 15, 2023 16:18 3m 18s sasha/riscv/fmaddd
sasha/riscv/fmaddd
November 15, 2023 16:18 3m 18s
interactive: add "clear passes button" (2/7) CI - MLIR-based Testing #6741: Pull request #1789 synchronize by dshaaban01
November 15, 2023 16:04 5m 14s dalia/condense.1
dalia/condense.1
November 15, 2023 16:04 5m 14s
interactive: add "clear passes button" (2/7) CI - MLIR-based Testing #6740: Pull request #1789 opened by dshaaban01
November 15, 2023 15:57 1m 15s dalia/condense.1
dalia/condense.1
November 15, 2023 15:57 1m 15s
interactive: change to ListView (1/7) CI - MLIR-based Testing #6739: Pull request #1788 opened by dshaaban01
November 15, 2023 15:19 3m 6s dalia/condense
dalia/condense
November 15, 2023 15:19 3m 6s
misc: (Makefile) Use a better message for tests target CI - MLIR-based Testing #6738: Pull request #1787 opened by compor
November 15, 2023 15:11 5m 35s christos/misc/makefile-fix-weird-message
christos/misc/makefile-fix-weird-message
November 15, 2023 15:11 5m 35s
backend: (riscv) Exclude FP registers from RISC-V regalloc in the presence of snitch_stream IO ops CI - MLIR-based Testing #6737: Pull request #1786 synchronize by compor
November 15, 2023 14:59 3m 7s christos/backend/riscv/regalloc-exclude-regs-snrt-stream
christos/backend/riscv/regalloc-exclude-regs-snrt-stream
November 15, 2023 14:59 3m 7s
backend: (riscv) Exclude FP registers from RISC-V regalloc in the presence of snitch_stream IO ops CI - MLIR-based Testing #6736: Pull request #1786 synchronize by compor
November 15, 2023 14:18 6m 26s christos/backend/riscv/regalloc-exclude-regs-snrt-stream
christos/backend/riscv/regalloc-exclude-regs-snrt-stream
November 15, 2023 14:18 6m 26s
backend: (riscv) Exclude FP registers from RISC-V regalloc in the presence of snitch_stream IO ops CI - MLIR-based Testing #6735: Pull request #1786 opened by compor
November 15, 2023 14:17 3m 8s christos/backend/riscv/regalloc-exclude-regs-snrt-stream
christos/backend/riscv/regalloc-exclude-regs-snrt-stream
November 15, 2023 14:17 3m 8s
misc: Add a version flag to xdsl (#1785) CI - MLIR-based Testing #6734: Commit 4c04de0 pushed by AntonLydike
November 15, 2023 13:50 3m 2s main
main
November 15, 2023 13:50 3m 2s
misc: Add a version flag to xdsl CI - MLIR-based Testing #6733: Pull request #1785 synchronize by AntonLydike
November 15, 2023 13:27 3m 16s anton/add-version-flag
anton/add-version-flag
November 15, 2023 13:27 3m 16s
misc: Add a version flag to xdsl CI - MLIR-based Testing #6732: Pull request #1785 opened by AntonLydike
November 15, 2023 13:27 3m 16s anton/add-version-flag
anton/add-version-flag
November 15, 2023 13:27 3m 16s
dialects: (hw) Add InnerSymbolTable and InnerRefNamespace to HW dialect CI - MLIR-based Testing #6731: Pull request #1780 synchronize by lucjaulmes
November 15, 2023 13:03 3m 23s lucjaulmes:seq-hw-3
lucjaulmes:seq-hw-3
November 15, 2023 13:03 3m 23s