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backend: (riscv) Exclude FP registers from RISC-V regalloc in the presence of snitch_stream IO ops #1786

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merged 5 commits into from
Nov 16, 2023
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backend: (riscv) Exclude FP registers from RISC-V regalloc in the presence of snitch_stream IO ops #1786

merged 5 commits into from
Nov 16, 2023

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compor
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@compor compor commented Nov 15, 2023 •
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This PR adds:

  • Exclusion of FP registers (currently ft0-ft2) from RISC-V register allocation in the presence of snitch_stream IO ops (strided_read and strided_write).
  • Tests of the above functionality.

Resolves opencompl/riscv-paper-experiments#63

@compor compor added the backend Compiler backend in xDSL label Nov 15, 2023
@compor compor self-assigned this Nov 15, 2023
@compor compor changed the title backend: (riscv) Exclude FP registers from RISC-V register allocation in the presence of snitch_stream IO ops backend: (riscv) Exclude FP registers from RISC-V regalloc in the presence of snitch_stream IO ops Nov 15, 2023
@compor compor requested a review from AntonLydike November 15, 2023 14:20
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codecov bot commented Nov 15, 2023 •
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Codecov Report

Attention: 1 lines in your changes are missing coverage. Please review.

Comparison is base (4c04de0) 88.90% compared to head (3e4d9ba) 88.91%.

Files Patch % Lines
xdsl/backend/riscv/register_allocation.py 93.75% 0 Missing and 1 partial ⚠️
Additional details and impacted files 
@@            Coverage Diff             @@
##             main    #1786      +/-   ##
==========================================
+ Coverage   88.90%   88.91%   +0.01%     
==========================================
  Files         260      260              
  Lines       32050    32064      +14     
  Branches     4725     4728       +3     
==========================================
+ Hits        28495    28511      +16     
+ Misses       2862     2861       -1     
+ Partials      693      692       -1

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superlopuh
superlopuh approved these changes Nov 15, 2023
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Looks great

xdsl/transforms/snitch_register_allocation.py Outdated Show resolved Hide resolved
xdsl/backend/riscv/register_allocation.py Outdated Show resolved Hide resolved
@compor compor added the transformations Changes or adds a transformatio label Nov 15, 2023
@compor compor merged commit e041198 into main Nov 16, 2023
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@compor compor deleted the christos/backend/riscv/regalloc-exclude-regs-snrt-stream branch November 16, 2023 08:35
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@adutilleul adutilleul adutilleul approved these changes

@superlopuh superlopuh superlopuh approved these changes

@nazavode nazavode Awaiting requested review from nazavode

@JosseVanDelm JosseVanDelm Awaiting requested review from JosseVanDelm

@AntonLydike AntonLydike Awaiting requested review from AntonLydike

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Successfully merging this pull request may close these issues.

Exclude registers ft0-ft2 from the list of available registers if there's a snitch stream in the block
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@compor @superlopuh @adutilleul