dialects: (riscv) add double-precision fmadd and fmsub (#1790)

xdslproject · Nov 16, 2023 · 4b87e5b · 4b87e5b
1 parent e041198
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diff --git a/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir b/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir
@@ -257,6 +257,10 @@
     riscv.fsd %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<j5>) -> ()
     // CHECK-NEXT: fsd j5, 1(zero)
 
+    %fmadd_d = riscv.fmadd.d %f0, %f1, %f2 : (!riscv.freg<j5>, !riscv.freg<j6>, !riscv.freg<j7>) -> !riscv.freg<j8>
+    // CHECK-NEXT: fmadd.d j8, j5, j6, j7
+    %fmsub_d = riscv.fmsub.d %f0, %f1, %f2 : (!riscv.freg<j5>, !riscv.freg<j6>, !riscv.freg<j7>) -> !riscv.freg<j8>
+    // CHECK-NEXT: fmsub.d j8, j5, j6, j7
     %fadd_d= riscv.fadd.d %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>
     // CHECK-NEXT: fadd.d j8, j5, j6
     %fsub_d = riscv.fsub.d %f0, %f1 : (!riscv.freg<j5>, !riscv.freg<j6>) -> !riscv.freg<j8>

diff --git a/tests/filecheck/dialects/riscv/riscv_ops.mlir b/tests/filecheck/dialects/riscv/riscv_ops.mlir
@@ -285,6 +285,11 @@
 
     // RV32F: 9 “D” Standard Extension for Single-Precision Floating-Point, Version 2.0
 
+    %fmadd_d = riscv.fmadd.d %f0, %f1, %f2 : (!riscv.freg<>, !riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
+    // CHECK-NEXT: %{{.*}} = riscv.fmadd.d %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg<>, !riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
+    %fmsub_d = riscv.fmsub.d %f0, %f1, %f2 : (!riscv.freg<>, !riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
+    // CHECK-NEXT: %{{.*}} = riscv.fmsub.d %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg<>, !riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
+
     %fmin_d = riscv.fmin.d %f0, %f1 : (!riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
     // CHECK-NEXT: %{{.*}} = riscv.fmin.d %{{.*}}, %{{.*}} : (!riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
     %fmax_d = riscv.fmax.d %f0, %f1 : (!riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
@@ -418,6 +423,8 @@
 // CHECK-GENERIC-NEXT:     "riscv.fsd"(%0, %f0) {"immediate" = 1 : si12} : (!riscv.reg<>, !riscv.freg<>) -> ()
 // CHECK-GENERIC-NEXT:     %vfadd_s = "riscv.vfadd.s"(%f0, %f1) : (!riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
 // CHECK-GENERIC-NEXT:     %vfmul_s = "riscv.vfmul.s"(%f0, %f1) : (!riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
+// CHECK-GENERIC-NEXT:     %fmadd_d = "riscv.fmadd.d"(%f0, %f1, %f2) : (!riscv.freg<>, !riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
+// CHECK-GENERIC-NEXT:     %fmsub_d = "riscv.fmsub.d"(%f0, %f1, %f2) : (!riscv.freg<>, !riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
 // CHECK-GENERIC-NEXT:     %fmin_d = "riscv.fmin.d"(%f0, %f1) : (!riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
 // CHECK-GENERIC-NEXT:     %fmax_d = "riscv.fmax.d"(%f0, %f1) : (!riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
 // CHECK-GENERIC-NEXT: %{{.*}} = "riscv.fcvt.d.w"(%{{.*}}) : (!riscv.reg<>) -> !riscv.freg<>

diff --git a/xdsl/dialects/riscv.py b/xdsl/dialects/riscv.py
@@ -3357,6 +3357,36 @@ def assembly_line(self) -> str | None:
 # region RV32F: 9 “D” Standard Extension for Double-Precision Floating-Point, Version 2.0
 
 
+@irdl_op_definition
+class FMAddDOp(RdRsRsRsFloatOperation):
+    """
+    Perform double-precision fused multiply addition.
+
+    f[rd] = f[rs1]×f[rs2]+f[rs3]
+
+    https://msyksphinz-self.github.io/riscv-isadoc/html/rvfd.html#fmadd-d
+    """
+
+    name = "riscv.fmadd.d"
+
+    traits = frozenset((Pure(),))
+
+
+@irdl_op_definition
+class FMSubDOp(RdRsRsRsFloatOperation):
+    """
+    Perform double-precision fused multiply substraction.
+
+    f[rd] = f[rs1]×f[rs2]+f[rs3]
+
+    https://msyksphinz-self.github.io/riscv-isadoc/html/rvfd.html#fmsub-d
+    """
+
+    name = "riscv.fmsub.d"
+
+    traits = frozenset((Pure(),))
+
+
 @irdl_op_definition
 class FAddDOp(RdRsRsOperation[FloatRegisterType, FloatRegisterType, FloatRegisterType]):
     """
@@ -3715,6 +3745,8 @@ def _print_immediate_value(printer: Printer, immediate: AnyIntegerAttr | LabelAt
         FMvWXOp,
         FLwOp,
         FSwOp,
+        FMAddDOp,
+        FMSubDOp,
         FAddDOp,
         FSubDOp,
         FMulDOp,