optimize witness cloning #89
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circuit witness: direct witness on mle devirgo style on phase1_output
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* optimize sumcheck algo circuit witness: direct witness on mle devirgo style on phase1_output * initial version for new zkVM design * riscv add prototype implementation * add new zkVM prover * new package ceno_zkvm * record witness generation * add transcript * add verifier * code cleanup * rename expression * prover record_r/record_w sumcheck * main sel sumcheck proof/verify * tower product witness inference * tower product sumcheck prove/verify * chores: fix tower sumcheck witness length error and clean up * verify record and zero expression * tower sumcheck prove/verify pass * WIP test main sel prove/verify * add benchmark * chores: interleaving with default value * main constraint sumcheck prove/verify pass * chores: mock witness * main constraint sumcheck verify final claim assertion pass * restructure ceno_zkvm package * refine expression format * wip lookup * lookup in logup implemetation with integration test pass * chores: code cosmetics * optimize with 2-stage sumcheck #103 * chores: refine virtual polys naming * fix proper ts and pc counting * try sumcheck bench * refine global state in riscv * degree > 1 main constraint sumcheck implementation #107 (#108) * monomial expression to virtual poly * degree > 1 sumcheck batched with main constraint * succint selector evaluation * refine succint selector evaluation formula and documentation * wip fix interleaving edge case * deal with interleaving_mles instance = 1 case * chores: code cosmetics and address review comments * fix logup padding with chip record challenge * riscv opcode type & combine add/sub opcode & dependency trim * ci whitelist ceno_zkvm lint/clippy * address review comments and naming cosmetics * remove unnessesary to_vec operation * tower verifier logup p(x) constant check * cleanup and hide thread-based logic * soundness fix: derive new sumcheck batched challenge for each round * fix sel evaluation point and add TODO check * fix sumcheck batched challenge deriving order * chore: rename pc step size & fine tune project structure * fix lint error
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* optimize sumcheck algo circuit witness: direct witness on mle devirgo style on phase1_output * temporarily exclude singer-pro from default workspace members * fux build error in mpcs * [Experiment] new zkVM design (#91) * optimize sumcheck algo circuit witness: direct witness on mle devirgo style on phase1_output * initial version for new zkVM design * riscv add prototype implementation * add new zkVM prover * new package ceno_zkvm * record witness generation * add transcript * add verifier * code cleanup * rename expression * prover record_r/record_w sumcheck * main sel sumcheck proof/verify * tower product witness inference * tower product sumcheck prove/verify * chores: fix tower sumcheck witness length error and clean up * verify record and zero expression * tower sumcheck prove/verify pass * WIP test main sel prove/verify * add benchmark * chores: interleaving with default value * main constraint sumcheck prove/verify pass * chores: mock witness * main constraint sumcheck verify final claim assertion pass * restructure ceno_zkvm package * refine expression format * wip lookup * lookup in logup implemetation with integration test pass * chores: code cosmetics * optimize with 2-stage sumcheck #103 * chores: refine virtual polys naming * fix proper ts and pc counting * try sumcheck bench * refine global state in riscv * degree > 1 main constraint sumcheck implementation #107 (#108) * monomial expression to virtual poly * degree > 1 sumcheck batched with main constraint * succint selector evaluation * refine succint selector evaluation formula and documentation * wip fix interleaving edge case * deal with interleaving_mles instance = 1 case * chores: code cosmetics and address review comments * fix logup padding with chip record challenge * riscv opcode type & combine add/sub opcode & dependency trim * ci whitelist ceno_zkvm lint/clippy * address review comments and naming cosmetics * remove unnessesary to_vec operation * tower verifier logup p(x) constant check * cleanup and hide thread-based logic * soundness fix: derive new sumcheck batched challenge for each round * fix sel evaluation point and add TODO check * fix sumcheck batched challenge deriving order * chore: rename pc step size & fine tune project structure * fix lint error
This was referenced Oct 4, 2024
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Fixes #313 Commit 0a40721 from #89 broke `singer-pro`. At least judging by whether `cargo check` succeeds. It even has a commit about that [temporarily exclude singer-pro from default workspace members](5ec37ec). Please restore `singer-pro` from the git history, if/when you need it again. Also remove `singer/examples/add-v2-old-sc-bak.rs` which was broken by the same commit. The filename suggests it was kept around as a 'backup'? (Please, have some more faith in git's ability to keep history!)
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| const VALUE_BIT_WIDTH: usize = 16; | ||
| pub type WitnessId = u16; |
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Why did we go with u16 here?
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This PR applied a widely refactor, and the goals is to avoid wire_in/wire_out clone between GKR nodes during proving. The core ideas are to
DenseMultilinearExtensiondirectly as input wire_in, avoiding extra overhead ofLayerWitnessconversionRangedMultilinearExtensionwhich wraps a reference of mle, plus astart/offsetto specify which range belong to it. This can avoid layer poly creation per multi-threading.This PR tried to prepare for the foundation for potiential widely refactor required from
A preliminary test shows 1.5x throughtput improvement on
evm_addbenchmark under instance size 2^11 - 14