GND

The GND primitive is a logic low level generator, specifically producing a GND output. It has a single port named "G" that outputs GND, which is described as the logic low level. The GND primitive serves to generate this stable low-level voltage or signal.

This device is supported in Apicula.

Ports

Port	Size	Direction
G	1	output

Verilog Instantiation

GND gnd_inst (
    .G(G)
);