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Pepijn de Vos edited this page Nov 19, 2024 · 2 revisions

FLASH256K

The FLASH256K primitive has a size of 256 Kbits, with non-volatile and power-off saving functions. It supports page erasure (2048 bytes per page) and has a fixed width and depth. The column memory size is 32 bits, and one row is composed of 64 column memory cells, with a row memory size of 2048 bits.

This device is supported in Apicula.

Ports

Port Size Direction
DIN 32 input
DOUT 32 output
ERASE 1 input
NVSTR 1 input
PROG 1 input
SE 1 input
XADR 7 input
XE 1 input
YADR 6 input
YE 1 input

Parameters

Parameter Default Value
ERA_S1 1 (0b0001)
ERA_S2 2 (0b0010)
ERA_S3 3 (0b0011)
ERA_S4 4 (0b0100)
ERA_S5 5 (0b0101)
IDLE 0 (0b0000)
PRO_S1 6 (0b0110)
PRO_S2 7 (0b0111)
PRO_S3 8 (0b1000)
PRO_S4 9 (0b1001)
PRO_S5 10 (0b1010)
RD_S1 11 (0b1011)
RD_S2 12 (0b1100)

Verilog Instantiation

FLASH256K #(
    .ERA_S1(ERA_S1),
    .ERA_S2(ERA_S2),
    .ERA_S3(ERA_S3),
    .ERA_S4(ERA_S4),
    .ERA_S5(ERA_S5),
    .IDLE(IDLE),
    .PRO_S1(PRO_S1),
    .PRO_S2(PRO_S2),
    .PRO_S3(PRO_S3),
    .PRO_S4(PRO_S4),
    .PRO_S5(PRO_S5),
    .RD_S1(RD_S1),
    .RD_S2(RD_S2)
) flash256k_inst (
    .DIN(DIN),
    .DOUT(DOUT),
    .ERASE(ERASE),
    .NVSTR(NVSTR),
    .PROG(PROG),
    .SE(SE),
    .XADR(XADR),
    .XE(XE),
    .YADR(YADR),
    .YE(YE)
);

FLASH608K

The FLASH608K primitive has a size of 608 Kbits, is composed of row memory and column memory cells with one row being 64 column memory cells, supports page erasure of 2048 bytes per page, and has features including 10,000 write cycles, data retention for more than ten years at +85℃, a data width of 32 bits, and access and program times of 25ns (max) and 16μs (max), respectively.

This device is supported in Apicula.

Ports

Port Size Direction
DIN 32 input
DOUT 32 output
ERASE 1 input
NVSTR 1 input
PROG 1 input
SE 1 input
XADR 9 input
XE 1 input
YADR 6 input
YE 1 input

Parameters

Parameter Default Value
ERA_S1 1 (0b0001)
ERA_S2 2 (0b0010)
ERA_S3 3 (0b0011)
ERA_S4 4 (0b0100)
ERA_S5 5 (0b0101)
IDLE 0 (0b0000)
PRO_S1 6 (0b0110)
PRO_S2 7 (0b0111)
PRO_S3 8 (0b1000)
PRO_S4 9 (0b1001)
PRO_S5 10 (0b1010)
RD_S1 11 (0b1011)
RD_S2 12 (0b1100)

Verilog Instantiation

FLASH608K #(
    .ERA_S1(ERA_S1),
    .ERA_S2(ERA_S2),
    .ERA_S3(ERA_S3),
    .ERA_S4(ERA_S4),
    .ERA_S5(ERA_S5),
    .IDLE(IDLE),
    .PRO_S1(PRO_S1),
    .PRO_S2(PRO_S2),
    .PRO_S3(PRO_S3),
    .PRO_S4(PRO_S4),
    .PRO_S5(PRO_S5),
    .RD_S1(RD_S1),
    .RD_S2(RD_S2)
) flash608k_inst (
    .DIN(DIN),
    .DOUT(DOUT),
    .ERASE(ERASE),
    .NVSTR(NVSTR),
    .PROG(PROG),
    .SE(SE),
    .XADR(XADR),
    .XE(XE),
    .YADR(YADR),
    .YE(YE)
);

FLASH64K

The FLASH64K primitive has a size of 64 Kbits, with a fixed width and depth. It features non-volatile and power-off saving functions, but does not have an initial value. The primitive can enter sleep mode when SLEEP is high, and it supports 10,000 write cycles, data retention for more than 10 years at +85℃, and has 32 rows, 64 columns, and a 32-bit depth.

This device is supported in Apicula

Ports

Port Size Direction
DIN 32 input
DOUT 32 output
ERASE 1 input
NVSTR 1 input
PROG 1 input
SE 1 input
SLEEP 1 input
XADR 5 input
XE 1 input
YADR 6 input
YE 1 input

Parameters

Parameter Default Value
ERA_S1 1 (0b0001)
ERA_S2 2 (0b0010)
ERA_S3 3 (0b0011)
ERA_S4 4 (0b0100)
ERA_S5 5 (0b0101)
IDLE 0 (0b0000)
PRO_S1 6 (0b0110)
PRO_S2 7 (0b0111)
PRO_S3 8 (0b1000)
PRO_S4 9 (0b1001)
PRO_S5 10 (0b1010)
RD_S1 11 (0b1011)
RD_S2 12 (0b1100)

Verilog Instantiation

FLASH64K #(
    .ERA_S1(ERA_S1),
    .ERA_S2(ERA_S2),
    .ERA_S3(ERA_S3),
    .ERA_S4(ERA_S4),
    .ERA_S5(ERA_S5),
    .IDLE(IDLE),
    .PRO_S1(PRO_S1),
    .PRO_S2(PRO_S2),
    .PRO_S3(PRO_S3),
    .PRO_S4(PRO_S4),
    .PRO_S5(PRO_S5),
    .RD_S1(RD_S1),
    .RD_S2(RD_S2)
) flash64k_inst (
    .DIN(DIN),
    .DOUT(DOUT),
    .ERASE(ERASE),
    .NVSTR(NVSTR),
    .PROG(PROG),
    .SE(SE),
    .SLEEP(SLEEP),
    .XADR(XADR),
    .XE(XE),
    .YADR(YADR),
    .YE(YE)
);

FLASH64KZ

The Gowin FLASH64KZ primitive is a user Flash with a size of 64 Kbits, featuring non-volatile and power-off saving functions. It has 10,000 write cycles, supports page erasure (2,048 bytes per page), and has quick page erasure/write operation capabilities. The access time is 25ns (Max) and the program time is 16μs (Max). Additionally, it takes 120ms (Max) to erase a page, and its electric current varies depending on read or write/erase operations.

This device is supported in Apicula.

Ports

Port Size Direction
DIN 32 input
DOUT 32 output
ERASE 1 input
NVSTR 1 input
PROG 1 input
SE 1 input
XADR 5 input
XE 1 input
YADR 6 input
YE 1 input

Parameters

Parameter Default Value
ERA_S1 1 (0b0001)
ERA_S2 2 (0b0010)
ERA_S3 3 (0b0011)
ERA_S4 4 (0b0100)
ERA_S5 5 (0b0101)
IDLE 0 (0b0000)
PRO_S1 6 (0b0110)
PRO_S2 7 (0b0111)
PRO_S3 8 (0b1000)
PRO_S4 9 (0b1001)
PRO_S5 10 (0b1010)
RD_S1 11 (0b1011)
RD_S2 12 (0b1100)

Verilog Instantiation

FLASH64KZ #(
    .ERA_S1(ERA_S1),
    .ERA_S2(ERA_S2),
    .ERA_S3(ERA_S3),
    .ERA_S4(ERA_S4),
    .ERA_S5(ERA_S5),
    .IDLE(IDLE),
    .PRO_S1(PRO_S1),
    .PRO_S2(PRO_S2),
    .PRO_S3(PRO_S3),
    .PRO_S4(PRO_S4),
    .PRO_S5(PRO_S5),
    .RD_S1(RD_S1),
    .RD_S2(RD_S2)
) flash64kz_inst (
    .DIN(DIN),
    .DOUT(DOUT),
    .ERASE(ERASE),
    .NVSTR(NVSTR),
    .PROG(PROG),
    .SE(SE),
    .XADR(XADR),
    .XE(XE),
    .YADR(YADR),
    .YE(YE)
);

FLASH96K

FLASH96K has the following features.

  • 100,000 write cycles
  • Data retention for more than 10 years (+85℃)
  • 8/16/32 bits data-in and data-out
  • Size: 48 rows * 64 columns * 32 bits = 96 Kbits
  • Page size: 256 bytes
  • 3 μA standby current

This device is supported in Apicula

Ports

Port Size Direction
ACLK 1 input
CA 6 input
DIN 32 input
DOUT 32 output
MODE 4 input
OE 1 input
PA 6 input
PE 1 input
PW 1 input
RA 6 input
RBYTESEL 2 input
RESET 1 input
RMODE 2 input
SEQ 2 input
WBYTESEL 2 input
WMODE 2 input

Verilog Instantiation

FLASH96K flash96k_inst (
    .ACLK(ACLK),
    .CA(CA),
    .DIN(DIN),
    .DOUT(DOUT),
    .MODE(MODE),
    .OE(OE),
    .PA(PA),
    .PE(PE),
    .PW(PW),
    .RA(RA),
    .RBYTESEL(RBYTESEL),
    .RESET(RESET),
    .RMODE(RMODE),
    .SEQ(SEQ),
    .WBYTESEL(WBYTESEL),
    .WMODE(WMODE)
);

FLASH96KA

The FLASH96KA primitive has a size of 96 Kbits, supports sleep mode, has non-volatile and power-off save functions, and does not support initial value function. It is composed of row memory cells and column memory cells, with one row consisting of 64 column memory cells, each column being 32 bits. The row memory size is 2048 bits, and the primitive supports page erasure at 2048 bytes per page. Key features include 10,000 write cycles, data retention for over ten years, a 32-bit data width, and access times of up to 25ns with maximum program and page erase times of 16μs and 120ms respectively.

This device is not yet supported in Apicula

Ports

Port Size Direction
DIN 32 input
DOUT 32 output
ERASE 1 input
NVSTR 1 input
PROG 1 input
SE 1 input
SLEEP 1 input
XADR 6 input
XE 1 input
YADR 6 input
YE 1 input

Parameters

Parameter Default Value
ERA_S1 1 (0b0001)
ERA_S2 2 (0b0010)
ERA_S3 3 (0b0011)
ERA_S4 4 (0b0100)
ERA_S5 5 (0b0101)
IDLE 0 (0b0000)
PRO_S1 6 (0b0110)
PRO_S2 7 (0b0111)
PRO_S3 8 (0b1000)
PRO_S4 9 (0b1001)
PRO_S5 10 (0b1010)
RD_S1 11 (0b1011)
RD_S2 12 (0b1100)

Verilog Instantiation

FLASH96KA #(
    .ERA_S1(ERA_S1),
    .ERA_S2(ERA_S2),
    .ERA_S3(ERA_S3),
    .ERA_S4(ERA_S4),
    .ERA_S5(ERA_S5),
    .IDLE(IDLE),
    .PRO_S1(PRO_S1),
    .PRO_S2(PRO_S2),
    .PRO_S3(PRO_S3),
    .PRO_S4(PRO_S4),
    .PRO_S5(PRO_S5),
    .RD_S1(RD_S1),
    .RD_S2(RD_S2)
) flash96ka_inst (
    .DIN(DIN),
    .DOUT(DOUT),
    .ERASE(ERASE),
    .NVSTR(NVSTR),
    .PROG(PROG),
    .SE(SE),
    .SLEEP(SLEEP),
    .XADR(XADR),
    .XE(XE),
    .YADR(YADR),
    .YE(YE)
);
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