DCCG

The HCLK duty cycle correction module (DCCG) is a primitive that provides clock frequency correction, specifically supporting duty cycle correction. The DCCG has two ports: CLKIN for inputting the clock signal and CLKOUT for outputting the corrected clock signal. It also has a parameter called DCC_MODE with four possible values (2'b00, 2'b01, 2'b10, and 2'b11), which control different correction modes. The primitive supports various Gowin device series, including GW1N and GW1NR.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
CLKIN	1	input
CLKOUT	1	output

Parameters

Parameter	Default Value
DCC_MODE	0 (0b00)

Verilog Instantiation

DCCG #(
    .DCC_MODE(DCC_MODE)
) dccg_inst (
    .CLKIN(CLKIN),
    .CLKOUT(CLKOUT)
);