soc:arm:nxp_s32ze: Create MPU regions for separated code and data #80939
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The NXP s32ze board configs and mpu regions associate all code and data with the SRAM 0/1/ext of the architecture. There are 7 MBs of SRAMs per RTU which are dedicated to code use. Using them for the Zephyr flash target trips the MPU regions which assume a RODATA/TEXT endpoint as the beginning of the DATA/BSS section. Update to use the Code SRAMs for code and associate the MPU region with the data image start location. Signed-off-by: Matthew Christian <[email protected]>
zephyrbot
requested review from
bperseghetti,
Dat-NguyenDuy and
PetervdPerk-NXP
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Hi @mcc-terraline thanks for this contribution. Although your changes suggestion look good, NXP is working in a more comprehensive solution to allow executing Zephyr from CRAM through AXI-F read-only interface and using DRAM through AXI-M for data access. This relates to issue #60217 and it will allow to expand the SRAM memory available to Zephyr. We expect to have a pr opened soon, so I'd suggest to wait for this pr to be raised. |
@manuargue, thank you, I'll follow that issue and close this PR. |
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Hi @mcc-terraline, i have opened this PR: #81112, you can check it out. |
The NXP s32ze board configs and mpu regions associate all code and data with the SRAM 0/1/ext of the architecture. There are 7 MBs of SRAMs per RTU which are dedicated to code use. Using them for the Zephyr flash target trips the MPU regions which assume a RODATA/TEXT endpoint as the beginning of the DATA/BSS section. Update to use the Code SRAMs for code and associate the MPU region with the data image start location.