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Add support non-tile-multiple shard width #11435

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merged 12 commits into from
Dec 5, 2024

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nkpatel-tt
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@nkpatel-tt nkpatel-tt commented Aug 14, 2024

Ticket

[https://github.com//issues/10109]

Problem description

With tile multiple shard width, all cores might not be utilised which can degrade performance.

What's changed

Add non-tile multiple shard width support.

Checklist

@nkpatel-tt nkpatel-tt force-pushed the nkpatel/conv_op_non_tile_multiple_shard_widht branch 3 times, most recently from 2f7ba35 to 59c347a Compare August 15, 2024 10:18
@nkpatel-tt nkpatel-tt force-pushed the nkpatel/conv_op_non_tile_multiple_shard_widht branch from 59c347a to c4ebbe5 Compare August 20, 2024 20:19
Signed-off-by: Nilaykumar Patel <[email protected]>

tensor util changes

Signed-off-by: Nilaykumar Patel <[email protected]>

conv2d changes

Signed-off-by: Nilaykumar K Patel <[email protected]>

Normal test cases working with updated conv block config.

Signed-off-by: Nilaykumar K Patel <[email protected]>

kernel changes

Signed-off-by: Nilaykumar K Patel <[email protected]>

Resolve hang

Signed-off-by: Nilaykumar K Patel <[email protected]>

Clean up debug statements.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Clean up debug statements and functions.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Solve WS test hang.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Update input offset calculations based on alignment.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Align input matrix M for 1x1 conv according to new changes.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Fix after rebase

Signed-off-by: Nilaykumar K Patel <[email protected]>

Resolve Comments.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Remove Debug statements and commented code.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Changes with rebase.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Undo some changes after rebase-clenup

Signed-off-by: Nilaykumar K Patel <[email protected]>

Make pipeline work. Clean up needed.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Update input offset calculations based on alignment. Resolves maxpool and model pipeline failures.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Enable variable to support non-tile multiple width.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Divide tiles among cores instead of total height

Signed-off-by: Nilaykumar K Patel <[email protected]>

Modify Condition

Signed-off-by: Nilaykumar K Patel <[email protected]>

Change after latest rebase.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Modify test cases to accomodate small number of cores.

Signed-off-by: Nilaykumar Patel <[email protected]>

Resolve Yolo failure.

Signed-off-by: Nilaykumar Patel <[email protected]>

Add support for mulit-device tensor for weight and bias tensors.

Signed-off-by: Nilaykumar K Patel <[email protected]>

Add comment for prepare weight and bias matrix and modify condition.

Signed-off-by: Nilaykumar Patel <[email protected]>

Remove debug statements.

Signed-off-by: Nilaykumar Patel <[email protected]>

Address review comments

Signed-off-by: Nilaykumar Patel <[email protected]>
Signed-off-by: Nilaykumar Patel <[email protected]>
Signed-off-by: Nilaykumar Patel <[email protected]>
@nkpatel-tt nkpatel-tt force-pushed the nkpatel/conv_op_non_tile_multiple_shard_widht branch from 177f9f9 to bb48f05 Compare December 4, 2024 11:01
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must be moved to somewhere like tests/ttnn/unit_tests/gtests/

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there is no tt_eager, eventually all those tests must be moved out of the folder

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@ayerofieiev-tt
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Thank you, @TT-BrianLiu ! I agree, this is really important.

@@ -103,6 +120,8 @@ void kernel_main() {
constexpr uint32_t elem_nbytes = sizeof(uint16_t);
constexpr uint16_t pad_core_id = 0xFFFF;

uint32_t input_aligned_page_size = get_arg_val<uint32_t>(0);
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this should be a compile time arg

if constexpr (is_read) {
uint32_t dst_addr = out_base_l1_addr + dst_offset;
uint64_t src_addr = base_addr + src_offset;
noc_async_read(src_addr, dst_addr, size);
if (stick_nbytes == input_aligned_page_size) {
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please change this condition to use constexpr to make it compile time instead of current RT.

Signed-off-by: Nilaykumar Patel <[email protected]>
@nkpatel-tt nkpatel-tt merged commit a318130 into main Dec 5, 2024
168 of 171 checks passed
@nkpatel-tt nkpatel-tt deleted the nkpatel/conv_op_non_tile_multiple_shard_widht branch December 5, 2024 09:11
tt-rkim pushed a commit that referenced this pull request Dec 5, 2024
@nkpatel-tt nkpatel-tt restored the nkpatel/conv_op_non_tile_multiple_shard_widht branch December 5, 2024 13:33
yieldthought pushed a commit that referenced this pull request Dec 13, 2024
### Ticket
[#10109]

### Problem description
With tile multiple shard width, all cores might not be utilised which
can degrade performance.

### What's changed
Add non-tile multiple shard width support.

Signed-off-by: Nilaykumar K Patel <[email protected]>
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9 participants