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[!] fix sv names missmatch after rtlgen upgrade
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sergeykhbr committed Oct 30, 2024
1 parent 0874c3a commit b5de93b
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Showing 5 changed files with 6 additions and 5 deletions.
2 changes: 1 addition & 1 deletion sv/rtl/misclib/apb_prci.sv
Original file line number Diff line number Diff line change
Expand Up @@ -66,7 +66,7 @@ apb_slv #(

always_comb
begin: comb_proc
apb_prci_registers v;
apb_prci_rhegisters vh;
logic [31:0] vb_rdata;

vb_rdata = '0;
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2 changes: 1 addition & 1 deletion sv/rtl/riverlib/cache/lrunway.sv
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Expand Up @@ -46,7 +46,7 @@ lrunway_rxegisters rx, rxin;

always_comb
begin: comb_proc
lrunway_registers v;
lrunway_rxegisters vx;
logic [LINE_WIDTH-1:0] wb_tbl_rdata;
logic [abits-1:0] vb_tbl_wadr;
logic [LINE_WIDTH-1:0] vb_tbl_wdata_init;
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1 change: 1 addition & 0 deletions sv/rtl/riverlib/core/queue.sv
Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,7 @@ Queue_rxegisters rx, rxin;
always_comb
begin: comb_proc
Queue_registers v;
Queue_rxegisters vx;
logic nempty;
logic [dbits-1:0] vb_data_o;
logic full;
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2 changes: 1 addition & 1 deletion sv/rtl/riverlib/core/stacktrbuf.sv
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ StackTraceBuffer_rxegisters rx, rxin;

always_comb
begin: comb_proc
StackTraceBuffer_registers v;
StackTraceBuffer_rxegisters vx;
vx.raddr = rx.raddr;
for (int i = 0; i < STACK_TRACE_BUF_SIZE; i++) begin
vx.stackbuf[i] = rx.stackbuf[i];
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4 changes: 2 additions & 2 deletions sv/rtl/riverlib/dmi/jtagtap.sv
Original file line number Diff line number Diff line change
Expand Up @@ -108,8 +108,8 @@ jtagtap_rhegisters rh, rhin;

always_comb
begin: comb_proc
jtagtap_registers v;
jtagtap_nregisters nv;
jtagtap_nrhegisters nvh;
jtagtap_rhegisters vh;
logic [drlen-1:0] vb_dr;
logic v_dmi_req_valid;
logic v_dmi_req_write;
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