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[+] Update systemVerilog rtl generator to support multiple clock and …
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…reset signals per module. Split structure that previously contained registers with and without reset
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@sergeykhbr
sergeykhbr committed Oct 30, 2024
1 parent 70ede88 commit 0874c3a
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Showing 13 changed files with 277 additions and 245 deletions.
52 changes: 26 additions & 26 deletions sv/rtl/misclib/apb_prci.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -42,15 +42,15 @@ logic w_req_valid;
logic [31:0] wb_req_addr;
logic w_req_write;
logic [31:0] wb_req_wdata;
apb_prci_registers r, rin;
apb_prci_rhegisters rh, rhin;

apb_slv #(
.async_reset(async_reset),
.vid(VENDOR_OPTIMITECH),
.did(OPTIMITECH_PRCI)
) pslv0 (
.i_clk(i_clk),
.i_nrst(r.sys_nrst),
.i_nrst(rh.sys_nrst),
.i_mapinfo(i_mapinfo),
.o_cfg(o_cfg),
.i_apbi(i_apbi),
Expand All @@ -59,9 +59,9 @@ apb_slv #(
.o_req_addr(wb_req_addr),
.o_req_write(w_req_write),
.o_req_wdata(wb_req_wdata),
.i_resp_valid(r.resp_valid),
.i_resp_rdata(r.resp_rdata),
.i_resp_err(r.resp_err)
.i_resp_valid(rh.resp_valid),
.i_resp_rdata(rh.resp_rdata),
.i_resp_err(rh.resp_err)
);

always_comb
Expand All @@ -71,11 +71,11 @@ begin: comb_proc

vb_rdata = '0;

v = r;
vh = rh;

v.sys_rst = (i_pwrreset || (~i_sys_locked) || i_dmireset);
v.sys_nrst = (~(i_pwrreset || (~i_sys_locked) || i_dmireset));
v.dbg_nrst = (~(i_pwrreset || (~i_sys_locked)));
vh.sys_rst = (i_pwrreset || (~i_sys_locked) || i_dmireset);
vh.sys_nrst = (~(i_pwrreset || (~i_sys_locked) || i_dmireset));
vh.dbg_nrst = (~(i_pwrreset || (~i_sys_locked)));

// Registers access:
case (wb_req_addr[11: 2])
Expand All @@ -84,8 +84,8 @@ begin: comb_proc
vb_rdata[1] = i_ddr_locked;
end
10'd1: begin // 0x04: reset status
vb_rdata[0] = r.sys_nrst;
vb_rdata[1] = r.dbg_nrst;
vb_rdata[0] = rh.sys_nrst;
vb_rdata[1] = rh.dbg_nrst;
if (w_req_valid == 1'b1) begin
if (w_req_write == 1'b1) begin
// todo:
Expand All @@ -96,39 +96,39 @@ begin: comb_proc
end
endcase

v.resp_valid = w_req_valid;
v.resp_rdata = vb_rdata;
v.resp_err = 1'b0;
vh.resp_valid = w_req_valid;
vh.resp_rdata = vb_rdata;
vh.resp_err = 1'b0;

if (~async_reset && i_pwrreset == 1'b1) begin
v = apb_prci_r_reset;
vh = apb_prci_rh_reset;
end

o_sys_rst = r.sys_rst;
o_sys_nrst = r.sys_nrst;
o_dbg_nrst = r.dbg_nrst;
o_sys_rst = rh.sys_rst;
o_sys_nrst = rh.sys_nrst;
o_dbg_nrst = rh.dbg_nrst;

rin = v;
rhin = vh;
end: comb_proc


generate
if (async_reset) begin: async_rst_gen

always_ff @(posedge i_clk, posedge i_pwrreset) begin: rg_proc
always_ff @(posedge i_clk, posedge i_pwrreset) begin: rhg_proc
if (i_pwrreset == 1'b1) begin
r <= apb_prci_r_reset;
rh <= apb_prci_rh_reset;
end else begin
r <= rin;
rh <= rhin;
end
end: rg_proc
end: rhg_proc

end: async_rst_gen
else begin: no_rst_gen

always_ff @(posedge i_clk) begin: rg_proc
r <= rin;
end: rg_proc
always_ff @(posedge i_clk) begin: rhg_proc
rh <= rhin;
end: rhg_proc

end: no_rst_gen
endgenerate
Expand Down
4 changes: 2 additions & 2 deletions sv/rtl/misclib/apb_prci_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,9 +27,9 @@ typedef struct {
logic resp_valid;
logic [31:0] resp_rdata;
logic resp_err;
} apb_prci_registers;
} apb_prci_rhegisters;

const apb_prci_registers apb_prci_r_reset = '{
const apb_prci_rhegisters apb_prci_rh_reset = '{
1'b0, // sys_rst
1'b0, // sys_nrst
1'b0, // dbg_nrst
Expand Down
8 changes: 4 additions & 4 deletions sv/rtl/misclib/apb_uart.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -470,7 +470,7 @@ begin: comb_proc
v.err_stopbit = 1'b0;
v.fwcpuid = '0;
for (int i = 0; i < fifosz; i++) begin
v.rx_fifo[i] = '0;
v.rx_fifo[i] = 8'd0;
end
v.rx_state = idle;
v.rx_ena = 1'b0;
Expand All @@ -486,7 +486,7 @@ begin: comb_proc
v.rx_stop_cnt = 1'b0;
v.rx_shift = '0;
for (int i = 0; i < fifosz; i++) begin
v.tx_fifo[i] = '0;
v.tx_fifo[i] = 8'd0;
end
v.tx_state = idle;
v.tx_ena = 1'b0;
Expand Down Expand Up @@ -567,7 +567,7 @@ generate
r.err_stopbit <= 1'b0;
r.fwcpuid <= '0;
for (int i = 0; i < fifosz; i++) begin
r.rx_fifo[i] <= '0;
r.rx_fifo[i] <= 8'd0;
end
r.rx_state <= idle;
r.rx_ena <= 1'b0;
Expand All @@ -583,7 +583,7 @@ generate
r.rx_stop_cnt <= 1'b0;
r.rx_shift <= '0;
for (int i = 0; i < fifosz; i++) begin
r.tx_fifo[i] <= '0;
r.tx_fifo[i] <= 8'd0;
end
r.tx_state <= idle;
r.tx_ena <= 1'b0;
Expand Down
74 changes: 46 additions & 28 deletions sv/rtl/misclib/plic.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,13 @@ begin: comb_proc
logic [CFG_SYSBUS_DATA_BITS-1:0] vrdata;
logic [9:0] vb_irq_idx[0: ctxmax-1]; // Currently selected most prio irq
logic [9:0] vb_irq_prio[0: ctxmax-1]; // Currently selected prio level
plic_context_type vb_ctx[0: ctxmax-1];
logic [3:0] vb_ctx_priority_th[0: ctxmax-1];
logic [1023:0] vb_ctx_ie[0: ctxmax-1];
logic [(4 * 1024)-1:0] vb_ctx_ip_prio[0: ctxmax-1];
logic [15:0] vb_ctx_prio_mask[0: ctxmax-1];
logic [3:0] vb_ctx_sel_prio[0: ctxmax-1];
logic [9:0] vb_ctx_irq_idx[0: ctxmax-1];
logic [9:0] vb_ctx_irq_prio[0: ctxmax-1];
logic [(4 * 1024)-1:0] vb_src_priority;
logic [1023:0] vb_pending;
logic [ctxmax-1:0] vb_ip;
Expand All @@ -110,13 +116,25 @@ begin: comb_proc
vb_irq_prio[i] = '0;
end
for (int i = 0; i < ctxmax; i++) begin
vb_ctx[i].priority_th = 4'd0;
vb_ctx[i].ie = '0;
vb_ctx[i].ip_prio = '0;
vb_ctx[i].prio_mask = 16'd0;
vb_ctx[i].sel_prio = 4'd0;
vb_ctx[i].irq_idx = 10'd0;
vb_ctx[i].irq_prio = 10'd0;
vb_ctx_priority_th[i] = 4'd0;
end
for (int i = 0; i < ctxmax; i++) begin
vb_ctx_ie[i] = '0;
end
for (int i = 0; i < ctxmax; i++) begin
vb_ctx_ip_prio[i] = '0;
end
for (int i = 0; i < ctxmax; i++) begin
vb_ctx_prio_mask[i] = 16'd0;
end
for (int i = 0; i < ctxmax; i++) begin
vb_ctx_sel_prio[i] = 4'd0;
end
for (int i = 0; i < ctxmax; i++) begin
vb_ctx_irq_idx[i] = 10'd0;
end
for (int i = 0; i < ctxmax; i++) begin
vb_ctx_irq_prio[i] = 10'd0;
end
vb_src_priority = '0;
vb_pending = '0;
Expand All @@ -143,10 +161,10 @@ begin: comb_proc
vb_src_priority = r.src_priority;
vb_pending = r.pending;
for (int i = 0; i < ctxmax; i++) begin
vb_ctx[i].priority_th = r.ctx[i].priority_th;
vb_ctx[i].ie = r.ctx[i].ie;
vb_ctx[i].irq_idx = r.ctx[i].irq_idx;
vb_ctx[i].irq_prio = r.ctx[i].irq_prio;
vb_ctx_priority_th[i] = r.ctx[i].priority_th;
vb_ctx_ie[i] = r.ctx[i].ie;
vb_ctx_irq_idx[i] = r.ctx[i].irq_idx;
vb_ctx_irq_prio[i] = r.ctx[i].irq_prio;
end

for (int i = 1; i < irqmax; i++) begin
Expand All @@ -160,8 +178,8 @@ begin: comb_proc
if ((r.pending[i] == 1'b1)
&& (r.ctx[n].ie[i] == 1'b1)
&& (int'(r.src_priority[(4 * i) +: 4]) > r.ctx[n].priority_th)) begin
vb_ctx[n].ip_prio[(4 * i) +: 4] = r.src_priority[(4 * i) +: 4];
vb_ctx[n].prio_mask[int'(r.src_priority[(4 * i) +: 4])] = 1'b1;
vb_ctx_ip_prio[n][(4 * i) +: 4] = r.src_priority[(4 * i) +: 4];
vb_ctx_prio_mask[n][int'(r.src_priority[(4 * i) +: 4])] = 1'b1;
end
end
end
Expand All @@ -170,7 +188,7 @@ begin: comb_proc
for (int n = 0; n < ctxmax; n++) begin
for (int i = 0; i < 16; i++) begin
if (r.ctx[n].prio_mask[i] == 1'b1) begin
vb_ctx[n].sel_prio = i;
vb_ctx_sel_prio[n] = i;
end
end
end
Expand All @@ -188,8 +206,8 @@ begin: comb_proc
end

for (int n = 0; n < ctxmax; n++) begin
vb_ctx[n].irq_idx = vb_irq_idx[n];
vb_ctx[n].irq_prio = vb_irq_prio[n];
vb_ctx_irq_idx[n] = vb_irq_idx[n];
vb_ctx_irq_prio[n] = vb_irq_prio[n];
vb_ip[n] = (|vb_irq_idx[n]);
end

Expand Down Expand Up @@ -230,10 +248,10 @@ begin: comb_proc
vrdata = r.ctx[wb_req_addr[11: 7]].ie[(64 * wb_req_addr[6: 3]) +: 64];
if ((w_req_valid == 1'b1) && (w_req_write == 1'b1)) begin
if ((|wb_req_wstrb[3: 0]) == 1'b1) begin
vb_ctx[wb_req_addr[11: 7]].ie[(64 * wb_req_addr[6: 3]) +: 32] = wb_req_wdata[31: 0];
vb_ctx_ie[wb_req_addr[11: 7]][(64 * wb_req_addr[6: 3]) +: 32] = wb_req_wdata[31: 0];
end
if ((|wb_req_wstrb[7: 4]) == 1'b1) begin
vb_ctx[wb_req_addr[11: 7]].ie[((64 * wb_req_addr[6: 3]) + 32) +: 32] = wb_req_wdata[63: 32];
vb_ctx_ie[wb_req_addr[11: 7]][((64 * wb_req_addr[6: 3]) + 32) +: 32] = wb_req_wdata[63: 32];
end
end
end else if ((wb_req_addr[21: 12] >= 10'h200) && (wb_req_addr[20: 12] < ctxmax)) begin
Expand All @@ -248,11 +266,11 @@ begin: comb_proc
end
if ((w_req_valid == 1'b1) && (w_req_write == 1'b1)) begin
if ((|wb_req_wstrb[3: 0]) == 1'b1) begin
vb_ctx[rctx_idx].priority_th = wb_req_wdata[3: 0];
vb_ctx_priority_th[rctx_idx] = wb_req_wdata[3: 0];
end
if ((|wb_req_wstrb[7: 4]) == 1'b1) begin
// claim/ complete. Reading clears pedning bit
vb_ctx[rctx_idx].irq_idx = '0;
vb_ctx_irq_idx[rctx_idx] = '0;
end
end
end else begin
Expand All @@ -265,13 +283,13 @@ begin: comb_proc
v.pending = vb_pending;
v.ip = vb_ip;
for (int n = 0; n < ctxmax; n++) begin
v.ctx[n].priority_th = vb_ctx[n].priority_th;
v.ctx[n].ie = vb_ctx[n].ie;
v.ctx[n].ip_prio = vb_ctx[n].ip_prio;
v.ctx[n].prio_mask = vb_ctx[n].prio_mask;
v.ctx[n].sel_prio = vb_ctx[n].sel_prio;
v.ctx[n].irq_idx = vb_ctx[n].irq_idx;
v.ctx[n].irq_prio = vb_ctx[n].irq_prio;
v.ctx[n].priority_th = vb_ctx_priority_th[n];
v.ctx[n].ie = vb_ctx_ie[n];
v.ctx[n].ip_prio = vb_ctx_ip_prio[n];
v.ctx[n].prio_mask = vb_ctx_prio_mask[n];
v.ctx[n].sel_prio = vb_ctx_sel_prio[n];
v.ctx[n].irq_idx = vb_ctx_irq_idx[n];
v.ctx[n].irq_prio = vb_ctx_irq_prio[n];
end

if (~async_reset && i_nrst == 1'b0) begin
Expand Down
28 changes: 14 additions & 14 deletions sv/rtl/riverlib/cache/lrunway.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,9 +39,9 @@ localparam int LINE_WIDTH = (WAYS_TOTAL * waybits);
typedef struct {
logic [abits-1:0] radr;
logic [LINE_WIDTH-1:0] mem[0: LINES_TOTAL - 1];
} lrunway_registers;
} lrunway_rxegisters;

lrunway_registers r, rin;
lrunway_rxegisters rx, rxin;


always_comb
Expand All @@ -67,13 +67,13 @@ begin: comb_proc
shift_ena_up = 1'b0;
shift_ena_down = 1'b0;

v.radr = r.radr;
vx.radr = rx.radr;
for (int i = 0; i < LINES_TOTAL; i++) begin
v.mem[i] = r.mem[i];
vx.mem[i] = rx.mem[i];
end

v.radr = i_raddr;
wb_tbl_rdata = r.mem[int'(r.radr)];
vx.radr = i_raddr;
wb_tbl_rdata = rx.mem[int'(rx.radr)];

v_we = (i_up || i_down || i_init);

Expand Down Expand Up @@ -125,21 +125,21 @@ begin: comb_proc
end

if (v_we == 1'b1) begin
v.mem[int'(i_waddr)] = vb_tbl_wdata;
vx.mem[int'(i_waddr)] = vb_tbl_wdata;
end
o_lru = wb_tbl_rdata[(waybits - 1): 0];

rin.radr = v.radr;
rxin.radr = vx.radr;
for (int i = 0; i < LINES_TOTAL; i++) begin
rin.mem[i] = v.mem[i];
rxin.mem[i] = vx.mem[i];
end
end: comb_proc


always_ff @(posedge i_clk) begin: rg_proc
r.radr <= rin.radr;
always_ff @(posedge i_clk) begin: rxg_proc
rx.radr <= rxin.radr;
for (int i = 0; i < LINES_TOTAL; i++) begin
r.mem[i] <= rin.mem[i];
rx.mem[i] <= rxin.mem[i];
end
end: rg_proc
end: rxg_proc

endmodule: lrunway
8 changes: 4 additions & 4 deletions sv/rtl/riverlib/cache/pmp.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -105,8 +105,8 @@ begin: comb_proc

if (~async_reset && i_nrst == 1'b0) begin
for (int i = 0; i < CFG_PMP_TBL_SIZE; i++) begin
v.tbl[i].start_addr = '0;
v.tbl[i].end_addr = '0;
v.tbl[i].start_addr = 64'd0;
v.tbl[i].end_addr = 64'd0;
v.tbl[i].flags = 5'd0;
end
end
Expand All @@ -129,8 +129,8 @@ generate
always_ff @(posedge i_clk, negedge i_nrst) begin: rg_proc
if (i_nrst == 1'b0) begin
for (int i = 0; i < CFG_PMP_TBL_SIZE; i++) begin
r.tbl[i].start_addr <= '0;
r.tbl[i].end_addr <= '0;
r.tbl[i].start_addr <= 64'd0;
r.tbl[i].end_addr <= 64'd0;
r.tbl[i].flags <= 5'd0;
end
end else begin
Expand Down
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