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Implement SRL and SLL #304

Merged
merged 14 commits into from
Oct 8, 2024
Merged

Implement SRL and SLL #304

merged 14 commits into from
Oct 8, 2024

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zemse
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@zemse zemse commented Oct 3, 2024

Closes #282 and #123

@zemse zemse mentioned this pull request Oct 3, 2024
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@zemse zemse marked this pull request as ready for review October 4, 2024 04:24
@zemse zemse requested a review from hero78119 October 4, 2024 04:24
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@zemse zemse requested a review from KimiWu123 October 7, 2024 11:04
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hero78119 commented Oct 7, 2024

@KimiWu123 in this PR, Soham find a underconstrain situation, where we should constrain remainder < quotient.
This constrain will need to be delegate to caller for it's not covered in mul_add.

I think mul_add() is ok to just cover a = b * c + d without other logic.

Thus, I introduced DivConfig gadget in this new commit 39d7967
I thin divu also have the similar issue, so after this PR, we need to fix divu opcode to switch to use DivConfig as well

cc @zemse for review srli

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@KimiWu123 in this PR, Soham find a underconstrain situation, where we should constrain remainder < quotient. This constrain will need to be delegate to caller for it's not covered in mul_add.

I think mul_add() is ok to just cover a = b * c + d without other logic.

Thus, I introduced DivConfig gadget in this new commit 39d7967 I thin divu also have the similar issue, so after this PR, we need to fix divu opcode to switch to use DivConfig as well

cc @zemse for review srli

cite #132 #122

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@hero78119 hero78119 merged commit f7f0374 into scroll-tech:master Oct 8, 2024
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@zemse zemse deleted the srl branch October 8, 2024 07:14
hero78119 added a commit that referenced this pull request Oct 10, 2024
### Desc.
~~This PR is trying to integrate `DivConfig` introduced in #304 into
`divu` opcode. However,`DivConfig` fails when `divisor` is zero.~~

### Findings
~~`assert_less_than` should be `None` in this case since both of `lhs:
remainder` and `rhs: divisor` are witnesses and range-checked.~~

https://github.com/scroll-tech/ceno/blob/77a250c9e7988e6d126154c34396912721394dfe/ceno_zkvm/src/gadgets/div.rs#L44-L50

----
### Update
~~In the first place, this PR is trying to fix a failure when `divisor`
is zero. During fixing this issue, realized we don't really need
`DivConfig` since there are not much duplicated code between `SRL` and
`DIVU`. Therefore, we don't really need to "fix" this issue since it
works well on `SRL`. But I need to add "remainder < divisor" constraints
in `DIVU`.~~
I was trying to use `DivConfig` in this PR, but it made more complicated
code. So, the current version is only to add `remainder < divisor`
constraints in `divu`.

### Changes
- Fixing under constraints in `less_than`
- Adding "remainder < divisor" constraint in `divu`
- Adding some tests for `SRL` and `SLL`

---------

Co-authored-by: Ming <[email protected]>
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SRL
3 participants