Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Feat/#98 riscv mul opcode #219

Merged
merged 10 commits into from
Sep 18, 2024
Merged

Feat/#98 riscv mul opcode #219

merged 10 commits into from
Sep 18, 2024

Conversation

KimiWu123
Copy link
Contributor

close #98

@KimiWu123 KimiWu123 self-assigned this Sep 13, 2024
@KimiWu123 KimiWu123 force-pushed the feat/#98-riscv-mul-opcode branch from 1c0308e to 2bf7172 Compare September 13, 2024 06:20
@KimiWu123 KimiWu123 marked this pull request as ready for review September 13, 2024 06:21
@KimiWu123 KimiWu123 force-pushed the feat/#98-riscv-mul-opcode branch from 4d38b1e to 793c8e3 Compare September 13, 2024 06:54
@KimiWu123 KimiWu123 requested a review from hero78119 September 13, 2024 07:56
@KimiWu123 KimiWu123 force-pushed the feat/#98-riscv-mul-opcode branch from ee89708 to 7626e1c Compare September 16, 2024 05:40
hero78119
hero78119 reviewed Sep 16, 2024
View reviewed changes
Copy link
Collaborator

@hero78119 hero78119 left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

There are few build errors due to we switch to new constructor function StepRecord on master branch

ceno_zkvm/src/expression.rs Show resolved Hide resolved
ceno_zkvm/src/instructions/riscv/mul.rs Outdated Show resolved Hide resolved
ceno_zkvm/src/instructions/riscv/mul.rs Outdated Show resolved Hide resolved
ceno_zkvm/src/instructions/riscv/mul.rs Show resolved Hide resolved
@hero78119 hero78119 mentioned this pull request Sep 16, 2024
Closed
2 tasks
@hero78119
Copy link
Collaborator

It will be good to build the R-type inst based after #231, which can greatly cleaup quite of boilerplate code

@KimiWu123 KimiWu123 force-pushed the feat/#98-riscv-mul-opcode branch from 358ff09 to ec57ea9 Compare September 18, 2024 03:28
@KimiWu123 KimiWu123 requested a review from hero78119 September 18, 2024 06:38
hero78119
hero78119 approved these changes Sep 18, 2024
View reviewed changes
Copy link
Collaborator

@hero78119 hero78119 left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM!

@KimiWu123 KimiWu123 merged commit 713461b into master Sep 18, 2024
6 checks passed
@KimiWu123 KimiWu123 deleted the feat/#98-riscv-mul-opcode branch September 18, 2024 07:26
naure
naure reviewed Sep 20, 2024
View reviewed changes
ceno_emul/src/rv32im.rs
let insn = func7 << 25 | rs2 << 20 | rs1 << 15 | func3 << 12 | rd << 7 | opcode;
Self {
insn,
top_bit: func7 | 0x80,
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This is not right. See above:

top_bit: (insn & 0x80000000) >> 31,

hero78119 pushed a commit that referenced this pull request Sep 30, 2024
@KimiWu123 @hero78119
Feat/#98 riscv mul opcode (#219)
3e7efb9 
close #98
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@naure naure naure left review comments

@hero78119 hero78119 hero78119 approved these changes

Assignees

@KimiWu123 KimiWu123

Labels
opcode circuit
Projects
Ceno - Base VM
Status: Done
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.

riscv opcode mul implemetation
4 participants
@KimiWu123 @hero78119 @naure @kunxian-xia