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@KimiWu123
KimiWu123 committed Sep 17, 2024
1 parent 7626e1c commit 358ff09
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Showing 4 changed files with 60 additions and 83 deletions.
21 changes: 21 additions & 0 deletions ceno_emul/src/rv32im.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -197,6 +197,27 @@ impl DecodedInstruction {
}
}

pub fn from_raw(func7: u32, func3: u32, rs1: u32, rs2: u32, rd: u32, opcode: u32) -> Self {
// limit the range of inputs
let func7 = func7 & 0x7f; // 7bits mask
let rs2 = rs2 & 0x1f; // 5bits mask
let rs1 = rs1 & 0x1f;
let func3 = func3 & 0x07; // 3 bits mask
let rd = rd & 0x1f;
let opcode = opcode & 0x7f;
let insn = func7 << 25 | rs2 << 20 | rs1 << 15 | func3 << 12 | rd << 7 | opcode;
Self {
insn,
top_bit: func7 | 0x80,
func7,
rs2,
rs1,
func3,
rd,
opcode,
}
}

pub fn encoded(&self) -> u32 {
self.insn
}
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7 changes: 4 additions & 3 deletions ceno_emul/src/tracer.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,7 @@ impl StepRecord {
rs1_read: Word,
rs2_read: Word,
rd: Change<Word>,
previous_cycle: Cycle,
) -> StepRecord {
let insn = DecodedInstruction::new(insn_code);
StepRecord {
Expand All @@ -69,17 +70,17 @@ impl StepRecord {
rs1: Some(ReadOp {
addr: CENO_PLATFORM.register_vma(insn.rs1() as RegIdx).into(),
value: rs1_read,
previous_cycle: 0,
previous_cycle,
}),
rs2: Some(ReadOp {
addr: CENO_PLATFORM.register_vma(insn.rs2() as RegIdx).into(),
value: rs2_read,
previous_cycle: 0,
previous_cycle,
}),
rd: Some(WriteOp {
addr: CENO_PLATFORM.register_vma(insn.rd() as RegIdx).into(),
value: rd,
previous_cycle: 0,
previous_cycle,
}),
memory_op: None,
}
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4 changes: 4 additions & 0 deletions ceno_zkvm/src/instructions/riscv/addsub.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -322,6 +322,7 @@ mod test {
11,
0xfffffffe,
Change::new(0, 11_u32.wrapping_add(0xfffffffe)),
0,
)],
)
.unwrap();
Expand Down Expand Up @@ -364,6 +365,7 @@ mod test {
u32::MAX - 1,
u32::MAX - 1,
Change::new(0, (u32::MAX - 1).wrapping_add(u32::MAX - 1)),
0,
)],
)
.unwrap();
Expand Down Expand Up @@ -406,6 +408,7 @@ mod test {
11,
2,
Change::new(0, 11_u32.wrapping_sub(2)),
0,
)],
)
.unwrap();
Expand Down Expand Up @@ -448,6 +451,7 @@ mod test {
3,
11,
Change::new(0, 3_u32.wrapping_sub(11)),
0,
)],
)
.unwrap();
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111 changes: 31 additions & 80 deletions ceno_zkvm/src/instructions/riscv/mul.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -225,7 +225,7 @@ impl<E: ExtensionField> Instruction<E> for MulInstruction {

#[cfg(test)]
mod test {
use ceno_emul::{Change, ReadOp, StepRecord, WordAddr, WriteOp};
use ceno_emul::{ByteAddr, Change, DecodedInstruction, StepRecord, CENO_PLATFORM};
use goldilocks::GoldilocksExt2;
use itertools::Itertools;
use multilinear_extensions::mle::IntoMLEs;
Expand All @@ -248,35 +248,19 @@ mod test {
.unwrap();

// values assignment
let rs1 = Some(ReadOp {
addr: WordAddr::from(1),
value: 11u32,
previous_cycle: 2,
});
let rs2 = Some(ReadOp {
addr: WordAddr::from(2),
value: 2u32,
previous_cycle: 2,
});
let rd = Some(WriteOp {
addr: WordAddr::from(3),
value: Change {
before: 0u32,
after: 22u32,
},
previous_cycle: 2,
});

let inst = DecodedInstruction::from_raw(0b0000001, 0, 1, 2, 3, 0);
let (raw_witin, _) = MulInstruction::assign_instances(
&config,
cb.cs.num_witin as usize,
vec![StepRecord {
cycle: 3,
rs1,
rs2,
rd,
..Default::default()
}],
vec![StepRecord::new_r_instruction(
3,
ByteAddr(CENO_PLATFORM.pc_start()),
inst.encoded(),
11,
2,
Change::new(0, 22),
0,
)],
)
.unwrap();

Expand All @@ -302,35 +286,19 @@ mod test {
.unwrap();

// values assignment
let rs1 = Some(ReadOp {
addr: WordAddr::from(1),
value: u32::MAX / 2 + 1, // equals to 2^32 / 2
previous_cycle: 2,
});
let rs2 = Some(ReadOp {
addr: WordAddr::from(2),
value: 2u32,
previous_cycle: 2,
});
let rd = Some(WriteOp {
addr: WordAddr::from(3),
value: Change {
before: 0u32,
after: 0u32,
},
previous_cycle: 2,
});

let inst = DecodedInstruction::from_raw(0b0000001, 0, 1, 2, 3, 0);
let (raw_witin, _) = MulInstruction::assign_instances(
&config,
cb.cs.num_witin as usize,
vec![StepRecord {
cycle: 3,
rs1,
rs2,
rd,
..Default::default()
}],
vec![StepRecord::new_r_instruction(
3,
ByteAddr(CENO_PLATFORM.pc_start()),
inst.encoded(),
u32::MAX / 2 + 1,
2,
Change::new(0, 0),
0,
)],
)
.unwrap();

Expand All @@ -356,36 +324,19 @@ mod test {
.unwrap();

// values assignment
let rs1 = Some(ReadOp {
addr: WordAddr::from(1),
value: 4294901760u32, // equals [0, u16::MAX]
previous_cycle: 2,
});
let rs2 = Some(ReadOp {
addr: WordAddr::from(2),
value: 4294901760u32, // equals [0, u16::MAX]
previous_cycle: 2,
});
// 429490176 * 429490176 % 2^32 = 0
let rd = Some(WriteOp {
addr: WordAddr::from(3),
value: Change {
before: 0u32,
after: 0u32,
},
previous_cycle: 2,
});

let inst = DecodedInstruction::from_raw(0b0000001, 0, 1, 2, 3, 0);
let (raw_witin, _) = MulInstruction::assign_instances(
&config,
cb.cs.num_witin as usize,
vec![StepRecord {
cycle: 3,
rs1,
rs2,
rd,
..Default::default()
}],
vec![StepRecord::new_r_instruction(
3,
ByteAddr(CENO_PLATFORM.pc_start()),
inst.encoded(),
4294901760,
4294901760,
Change::new(0, 0),
0,
)],
)
.unwrap();

Expand Down

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