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Adding L2Cache Model - new sparta Unit #114

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merged 18 commits into from
Dec 6, 2023
+1,873 −33
Merged

Adding L2Cache Model - new sparta Unit #114

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69cfa15
Unit : L2Cache - new sparta unit that receives reqs from IL1 and DCAC…
Kunal-Buch Nov 3, 2023
3da0496
Unit : L2Cache - backpressure for biu credits and l2cache_pipeline_ -…
Kunal-Buch Nov 6, 2023
1e31d1c
Unit : L2Cache - fix for comments on PR , V1.0
Kunal-Buch Nov 9, 2023
903a38a
Merge branch 'riscv-software-src:master' into master
Kunal-Buch Nov 9, 2023
3ddda2f
Unit : L2Cache - V1.0 - comment fixes - make regress clean
Kunal-Buch Nov 9, 2023
c194936
initializing src_ and dest_ inline
Kunal-Buch Nov 9, 2023
9361306
Unit : L2Cache - V1.1 - comment fixes for IL1 changed to ICache,
Kunal-Buch Nov 9, 2023
9030a77
Merge remote-tracking branch 'origin'
Kunal-Buch Nov 9, 2023
c5f5d5d
Merge branch 'riscv-software-src:master' into master
Kunal-Buch Nov 9, 2023
9ea6662
Merge remote-tracking branch 'origin'
Kunal-Buch Nov 9, 2023
d317cf1
Unit : L2Cache - V1.1 - absorbing 'CacheFuncModel' name change
Kunal-Buch Nov 9, 2023
3b4a2f4
Unit : L2Cache - credit management between DCACHE<->L2CACHE<->BIU wit…
Kunal-Buch Nov 16, 2023
595e427
Merge branch 'riscv-software-src:master' into master
Kunal-Buch Nov 16, 2023
150b1c9
Unit : L2Cache - ack protocol change to credits, interface type change
Kunal-Buch Nov 17, 2023
b162610
Merge remote-tracking branch 'origin/master'
Kunal-Buch Nov 17, 2023
3da074d
Unit : L2Cache - using SSP instead of std::shared_ptr
Kunal-Buch Nov 21, 2023
d99f35b
Unit : L2Cache - linking misses to the same cacheline through next_re…
Kunal-Buch Nov 21, 2023
44345e9
Unit : L2Cache - removing unsed variable
Kunal-Buch Dec 4, 2023
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4 changes: 4 additions & 0 deletions core/CPUFactories.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@
#include "MMU.hpp"
#include "SimpleTLB.hpp"
#include "BIU.hpp"
#include "L2Cache.hpp"
#include "MSS.hpp"
#include "ROB.hpp"
#include "FlushManager.hpp"
Expand Down Expand Up @@ -71,6 +72,9 @@ namespace olympia{
sparta::ResourceFactory<olympia::LSU,
olympia::LSU::LSUParameterSet> lsu_rf;

//! \brief Resouce Factory to build a L2Cache Unit
sparta::ResourceFactory<olympia_mss::L2Cache,
olympia_mss::L2Cache::L2CacheParameterSet> l2cache_rf;

//! \brief Resouce Factory to build a BIU Unit
sparta::ResourceFactory<olympia_mss::BIU,
Expand Down
28 changes: 26 additions & 2 deletions core/CPUTopology.cpp
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Expand Up @@ -101,6 +101,14 @@ olympia::CoreTopologySimple::CoreTopologySimple(){
sparta::TreeNode::GROUP_IDX_NONE,
&factories->lsu_rf
},
{
"l2cache",
"cpu.core*",
"L2Cache Unit",
sparta::TreeNode::GROUP_NAME_NONE,
sparta::TreeNode::GROUP_IDX_NONE,
&factories->l2cache_rf
},
{
"biu",
"cpu.core*",
Expand Down Expand Up @@ -202,12 +210,28 @@ olympia::CoreTopologySimple::CoreTopologySimple(){
"cpu.core*.lsu.ports.in_cache_free_req"
},
{
"cpu.core*.dcache.ports.out_biu_req",
"cpu.core*.dcache.ports.out_l2cache_req",
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Can we add a L2Cache.md file documenting modeled microarchitcture of L2Cache? Such a document would help in understanding the code, and would enable new users and higher adoption by the community.

For example, it can include:

  • a description of various ports of L2Cache and their intended purpose
  • various structures and pipelines used in L2cache
  • stage by stage behavior of each pipeline

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Sure Arup.

Where should this L2Cache.md file reside?
I already have the info available in the presentation I prepared. Just need to port it over! :)

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I don't have an opinion on what would be the right place for it. Please feel free to create a dir called 'example_uarch_doc' and populate that with this README.

"cpu.core*.l2cache.ports.in_dcache_l2cache_req"
},
{
"cpu.core*.dcache.ports.in_l2cache_ack",
"cpu.core*.l2cache.ports.out_l2cache_dcache_ack"
},
{
"cpu.core*.dcache.ports.in_l2cache_resp",
"cpu.core*.l2cache.ports.out_l2cache_dcache_resp"
},
{
"cpu.core*.l2cache.ports.out_l2cache_biu_req",
"cpu.core*.biu.ports.in_biu_req"
},
{
"cpu.core*.biu.ports.out_biu_ack",
"cpu.core*.dcache.ports.in_biu_ack"
"cpu.core*.l2cache.ports.in_biu_l2cache_ack"
},
{
"cpu.core*.biu.ports.out_biu_resp",
"cpu.core*.l2cache.ports.in_biu_l2cache_resp"
},
{
"cpu.core*.lsu.ports.out_mmu_lookup_req",
Expand Down
15 changes: 11 additions & 4 deletions core/DCache.cpp
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Expand Up @@ -11,8 +11,11 @@ namespace olympia {
in_lsu_lookup_req_.registerConsumerHandler
(CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getInstsFromLSU_, MemoryAccessInfoPtr));

in_biu_ack_.registerConsumerHandler
(CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getAckFromBIU_, InstPtr));
in_l2cache_ack_.registerConsumerHandler
(CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getAckFromL2Cache_, bool));

in_l2cache_resp_.registerConsumerHandler
(CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getRespFromL2Cache_, InstPtr));

// DL1 cache config
const uint32_t l1_line_size = p->l1_line_size;
Expand Down Expand Up @@ -78,17 +81,21 @@ namespace olympia {
if(!busy_) {
busy_ = true;
cache_pending_inst_ = memory_access_info_ptr;
out_biu_req_.send(cache_pending_inst_->getInstPtr());
out_l2cache_req_.send(cache_pending_inst_->getInstPtr());
}
}
out_lsu_lookup_ack_.send(memory_access_info_ptr);
}

void DCache::getAckFromBIU_(const InstPtr &inst_ptr) {
void DCache::getRespFromL2Cache_(const InstPtr &inst_ptr) {
out_lsu_lookup_req_.send(cache_pending_inst_);
reloadCache_(inst_ptr->getRAdr());
cache_pending_inst_.reset();
busy_ = false;
}

void DCache::getAckFromL2Cache_(const bool &ack) {
// Process ACK
}
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}
15 changes: 10 additions & 5 deletions core/DCache.hpp
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Expand Up @@ -35,7 +35,9 @@ namespace olympia {

void getInstsFromLSU_(const MemoryAccessInfoPtr &memory_access_info_ptr);

void getAckFromBIU_(const InstPtr &inst_ptr);
void getAckFromL2Cache_(const bool &ack);

void getRespFromL2Cache_(const InstPtr &inst_ptr);

using L1Handle = SimpleDL1::Handle;
L1Handle l1_cache_;
Expand All @@ -51,8 +53,11 @@ namespace olympia {
sparta::DataInPort<MemoryAccessInfoPtr> in_lsu_lookup_req_
{&unit_port_set_, "in_lsu_lookup_req", 0};

sparta::DataInPort<InstPtr> in_biu_ack_
{&unit_port_set_, "in_biu_ack", 1};
sparta::DataInPort<bool> in_l2cache_ack_
{&unit_port_set_, "in_l2cache_ack", 1};
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sparta::DataInPort<InstPtr> in_l2cache_resp_
{&unit_port_set_, "in_l2cache_resp", 1};

////////////////////////////////////////////////////////////////////////////////
// Output Ports
Expand All @@ -66,8 +71,8 @@ namespace olympia {
sparta::DataOutPort<MemoryAccessInfoPtr> out_lsu_lookup_req_
{&unit_port_set_, "out_lsu_lookup_req", 1};

sparta::DataOutPort<InstPtr> out_biu_req_
{&unit_port_set_, "out_biu_req"};
sparta::DataOutPort<InstPtr> out_l2cache_req_
{&unit_port_set_, "out_l2cache_req"};

////////////////////////////////////////////////////////////////////////////////
// Events
Expand Down
27 changes: 27 additions & 0 deletions core/LSU.hpp
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Expand Up @@ -399,6 +399,30 @@ namespace olympia

};

inline std::ostream & operator<<(std::ostream & os,
const olympia::MemoryAccessInfo::UnitName & unit) {
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switch(unit) {
case olympia::MemoryAccessInfo::UnitName::IL1:
os << "IL1";
break;
case olympia::MemoryAccessInfo::UnitName::LSU:
os << "LSU";
break;
case olympia::MemoryAccessInfo::UnitName::DCACHE:
os << "DCACHE";
break;
case olympia::MemoryAccessInfo::UnitName::L2CACHE:
os << "L2CACHE";
break;
case olympia::MemoryAccessInfo::UnitName::BIU:
os << "BIU";
break;
default:
throw sparta::SpartaException("NUM_STATES cannot be a valid enum state.");
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}
return os;
}

inline std::ostream & operator<<(std::ostream & os,
const olympia::MemoryAccessInfo::MMUState & mmu_access_state){
switch(mmu_access_state){
Expand All @@ -423,6 +447,9 @@ namespace olympia
case olympia::MemoryAccessInfo::CacheState::NO_ACCESS:
os << "no_access";
break;
case olympia::MemoryAccessInfo::CacheState::RELOAD:
os << "reload";
break;
case olympia::MemoryAccessInfo::CacheState::MISS:
os << "miss";
break;
Expand Down
27 changes: 26 additions & 1 deletion core/MemoryAccessInfo.hpp
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Expand Up @@ -33,12 +33,25 @@ namespace olympia {
enum class CacheState : std::uint64_t {
NO_ACCESS = 0,
__FIRST = NO_ACCESS,
RELOAD,
MISS,
HIT,
NUM_STATES,
__LAST = NUM_STATES
};

enum class UnitName : std::uint32_t {
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NO_ACCESS = 0,
__FIRST = NO_ACCESS,
IL1,
LSU,
DCACHE,
L2CACHE,
BIU,
NUM_UNITS,
__LAST = NUM_UNITS
};

MemoryAccessInfo() = delete;

MemoryAccessInfo(
Expand All @@ -48,7 +61,9 @@ namespace olympia {
mmu_access_state_(MMUState::NO_ACCESS),

// Construct the State object here
cache_access_state_(CacheState::NO_ACCESS) {}
cache_access_state_(CacheState::NO_ACCESS),
src_(UnitName::IL1),
dest_(UnitName::BIU) {}

virtual ~MemoryAccessInfo() {}

Expand All @@ -67,6 +82,12 @@ namespace olympia {

bool getPhyAddrStatus() const { return phy_addr_ready_; }

void setSrcUnit(UnitName src_unit) { src_ = src_unit; }
const UnitName & getSrcUnit() const { return src_; }

void setDestUnit(UnitName dest_unit) { dest_ = dest_unit; }
const UnitName & getDestUnit() const { return dest_; }
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MMUState getMMUState() const {
return mmu_access_state_;
}
Expand Down Expand Up @@ -100,6 +121,10 @@ namespace olympia {
// DCache access status
CacheState cache_access_state_;

// Src and destination unit name for the packet
UnitName src_;
UnitName dest_;
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// Scoreboards
using ScoreboardViews = std::array<std::unique_ptr<sparta::ScoreboardView>, core_types::N_REGFILES>;
ScoreboardViews scoreboard_views_;
Expand Down
11 changes: 6 additions & 5 deletions mss/BIU.cpp
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Expand Up @@ -19,7 +19,7 @@ namespace olympia_mss
biu_latency_(p->biu_latency)
{
in_biu_req_.registerConsumerHandler
(CREATE_SPARTA_HANDLER_WITH_DATA(BIU, getReqFromLSU_, olympia::InstPtr));
(CREATE_SPARTA_HANDLER_WITH_DATA(BIU, getReqFromL2Cache_, olympia::InstPtr));

in_mss_ack_sync_.registerConsumerHandler
(CREATE_SPARTA_HANDLER_WITH_DATA(BIU, getAckFromMSS_, bool));
Expand All @@ -34,8 +34,8 @@ namespace olympia_mss
// Callbacks
////////////////////////////////////////////////////////////////////////////////

// Receive new BIU request from LSU
void BIU::getReqFromLSU_(const olympia::InstPtr & inst_ptr)
// Receive new BIU request from L2Cache
void BIU::getReqFromL2Cache_(const olympia::InstPtr & inst_ptr)
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{
appendReqQueue_(inst_ptr);

Expand Down Expand Up @@ -69,7 +69,9 @@ namespace olympia_mss
// Handle MSS Ack
void BIU::handle_MSS_Ack_()
{
out_biu_ack_.send(biu_req_queue_.front());
out_biu_resp_.send(biu_req_queue_.front(), biu_latency_);
out_biu_ack_.send(true);

biu_req_queue_.pop_front();
biu_busy_ = false;

Expand Down Expand Up @@ -97,7 +99,6 @@ namespace olympia_mss
sparta_assert(false, "MSS is NOT done!");
}


////////////////////////////////////////////////////////////////////////////////
// Regular Function/Subroutine Call
////////////////////////////////////////////////////////////////////////////////
Expand Down
11 changes: 7 additions & 4 deletions mss/BIU.hpp
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Expand Up @@ -67,9 +67,12 @@ namespace olympia_mss
// Output Ports
////////////////////////////////////////////////////////////////////////////////

sparta::DataOutPort<olympia::InstPtr> out_biu_ack_
sparta::DataOutPort<bool> out_biu_ack_
{&unit_port_set_, "out_biu_ack"};

sparta::DataOutPort<olympia::InstPtr> out_biu_resp_
{&unit_port_set_, "out_biu_resp"};

sparta::SyncOutPort<olympia::InstPtr> out_mss_req_sync_
{&unit_port_set_, "out_mss_req_sync", getClock()};

Expand All @@ -91,7 +94,7 @@ namespace olympia_mss
// Event Handlers
////////////////////////////////////////////////////////////////////////////////

// Event to handle BIU request from LSU
// Event to handle BIU request from L2Cache
sparta::UniqueEvent<> ev_handle_biu_req_
{&unit_event_set_, "handle_biu_req", CREATE_SPARTA_HANDLER(BIU, handle_BIU_Req_)};

Expand All @@ -104,8 +107,8 @@ namespace olympia_mss
// Callbacks
////////////////////////////////////////////////////////////////////////////////

// Receive new BIU request from LSU
void getReqFromLSU_(const olympia::InstPtr &);
// Receive new BIU request from L2Cache
void getReqFromL2Cache_(const olympia::InstPtr &);

// Handle BIU request
void handle_BIU_Req_();
Expand Down
1 change: 1 addition & 0 deletions mss/CMakeLists.txt
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@@ -1,6 +1,7 @@
project (mss)
add_library(mss
BIU.cpp
L2Cache.cpp
MSS.cpp
)
get_property(SPARTA_INCLUDE_PROP TARGET SPARTA::sparta PROPERTY INTERFACE_INCLUDE_DIRECTORIES)
Expand Down
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