Adding L2Cache Model - new sparta Unit #114
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…HE and sends out miss requests to the BIU
… make regress clean
Co-authored-by: Knute <[email protected]> Signed-off-by: Kunal-Buch <[email protected]>
UnitName remanmed to ArchUnit, and pre-incremnt for counters.
ghost
requested review from
| @@ -202,12 +210,28 @@ olympia::CoreTopologySimple::CoreTopologySimple(){ | |||
| "cpu.core*.lsu.ports.in_cache_free_req" | |||
| }, | |||
| { | |||
| "cpu.core*.dcache.ports.out_biu_req", | |||
| "cpu.core*.dcache.ports.out_l2cache_req", | |||
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Can we add a L2Cache.md file documenting modeled microarchitcture of L2Cache? Such a document would help in understanding the code, and would enable new users and higher adoption by the community.
For example, it can include:
- a description of various ports of L2Cache and their intended purpose
- various structures and pipelines used in L2cache
- stage by stage behavior of each pipeline
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Sure Arup.
Where should this L2Cache.md file reside?
I already have the info available in the presentation I prepared. Just need to port it over! :)
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I don't have an opinion on what would be the right place for it. Please feel free to create a dir called 'example_uarch_doc' and populate that with this README.
from bool to uint32_t + PR comment fixes. make regress clean.
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Hello @arupc , @klingaard ,: I have reviewed all the comments for the pull request above and provided the updates for all of them through the commits listed here. Is there anything else that remains to be reviewed/updated? |
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@h0lyalg0rithm you might need to see how this impacts your current PR |
-> L2Cache can accept multiple requests from DCache and IL1.
-> Cache functional model used is SimpleDL1.
-> Configurable cache hit latency.
-> Misses are forwarded to BIU and kept are tracked in the local buffer.
-> Miss to the pending cacheline is not sent out to BIU.
-> Backpressure handling for BIU credits.
-> make regress clean.