HyperRAMClkFreq expanded from HRClkFreq

lowRISC · Nov 14, 2024 · dbd482b · dbd482b
1 parent bcfdf6e
commit dbd482b
Show file tree

Hide file tree

Showing 5 changed files with 27 additions and 27 deletions.
diff --git a/dv/verilator/top_verilator.sv b/dv/verilator/top_verilator.sv
@@ -9,7 +9,7 @@ module top_verilator (input logic clk_i, rst_ni);
   // System clock frequency.
   localparam int unsigned SysClkFreq = 40_000_000;
   // HyperRAM clock frequency.
-  localparam int unsigned HRClkFreq  = 100_000_000;
+  localparam int unsigned HyperRAMClkFreq  = 100_000_000;
   localparam int unsigned BaudRate   = 921_600;
   // Number of CHERI error LEDs.
   localparam int unsigned CheriErrWidth = 9;
@@ -299,7 +299,7 @@ module top_verilator (input logic clk_i, rst_ni);
   sonata_system #(
     .CheriErrWidth   ( CheriErrWidth   ),
     .SysClkFreq      ( SysClkFreq      ),
-    .HRClkFreq       ( HRClkFreq       )
+    .HyperRAMClkFreq ( HyperRAMClkFreq )
   ) u_sonata_system (
     // Main system clock and reset
     .clk_sys_i      (clk_i),

diff --git a/rtl/fpga/clkgen_sonata.sv b/rtl/fpga/clkgen_sonata.sv
@@ -4,11 +4,11 @@
 
 module clkgen_sonata  #(
   // System Clock Frequency is parameterised, allowing it to be adjusted.
-  parameter int unsigned SysClkFreq = 50_000_000,
-  parameter int unsigned HRClkFreq  = 100_000_000,
+  parameter int unsigned SysClkFreq      =  50_000_000,
+  parameter int unsigned HyperRAMClkFreq = 100_000_000,
 
   // Frequency of IO_CLK input on the FPGA board.
-  parameter int unsigned IOClkFreq = 25_000_000
+  parameter int unsigned IOClkFreq       =  25_000_000
 ) (
     // Board clock signal
     input IO_CLK,
@@ -67,15 +67,15 @@ module clkgen_sonata  #(
     .CLKOUT1_PHASE        (0.000),
     .CLKOUT1_DUTY_CYCLE   (0.500),
 
-    .CLKOUT2_DIVIDE       ((48 * IOClkFreq) / HRClkFreq),
+    .CLKOUT2_DIVIDE       ((48 * IOClkFreq) / HyperRAMClkFreq),
     .CLKOUT2_PHASE        (0.000),
     .CLKOUT2_DUTY_CYCLE   (0.500),
 
-    .CLKOUT3_DIVIDE       ((48 * IOClkFreq) / HRClkFreq),
+    .CLKOUT3_DIVIDE       ((48 * IOClkFreq) / HyperRAMClkFreq),
     .CLKOUT3_PHASE        (90.000),
     .CLKOUT3_DUTY_CYCLE   (0.500),
 
-    .CLKOUT4_DIVIDE       ((48 * IOClkFreq) / (HRClkFreq * 3)),
+    .CLKOUT4_DIVIDE       ((48 * IOClkFreq) / (HyperRAMClkFreq * 3)),
     .CLKOUT4_PHASE        (0.000),
     .CLKOUT4_DUTY_CYCLE   (0.500),
 

diff --git a/rtl/fpga/top_sonata.sv b/rtl/fpga/top_sonata.sv
@@ -202,8 +202,8 @@ module top_sonata
   import sonata_pkg::*;
 
   // System clock frequency.
-  parameter int unsigned SysClkFreq = 40_000_000;
-  parameter int unsigned HRClkFreq  = 100_000_000;
+  parameter int unsigned SysClkFreq      =  40_000_000;
+  parameter int unsigned HyperRAMClkFreq = 100_000_000;
 
   parameter SRAMInitFile    = "";
 
@@ -266,10 +266,10 @@ module top_sonata
   logic rs485_rx_enable, rs485_tx_enable;
 
   sonata_system #(
-    .CheriErrWidth   (  9             ),
-    .SRAMInitFile    ( SRAMInitFile   ),
-    .SysClkFreq      ( SysClkFreq     ),
-    .HRClkFreq       ( HRClkFreq      )
+    .CheriErrWidth   ( 9               ),
+    .SRAMInitFile    ( SRAMInitFile    ),
+    .SysClkFreq      ( SysClkFreq      ),
+    .HyperRAMClkFreq ( HyperRAMClkFreq )
   ) u_sonata_system (
     // Main system clock and reset
     .clk_sys_i      (clk_sys),
@@ -384,8 +384,8 @@ module top_sonata
 
   // Produce 50 MHz system clock from 25 MHz Sonata board clock.
   clkgen_sonata #(
-    .SysClkFreq(SysClkFreq),
-    .HRClkFreq (HRClkFreq)
+    .SysClkFreq      ( SysClkFreq      ),
+    .HyperRAMClkFreq ( HyperRAMClkFreq )
   ) u_clkgen(
     .IO_CLK    (mainClk),
     .IO_CLK_BUF(main_clk_buf),

diff --git a/rtl/ip/hyperram/rtl/hyperram.sv b/rtl/ip/hyperram/rtl/hyperram.sv
@@ -8,8 +8,8 @@
 // don't want to include the full hyperram controller RTL and BFM (which in
 // particular require Xilinx encrypted IP models).
 module hyperram import tlul_pkg::*; #(
-  parameter HRClkFreq    = 100_000_000,
-  parameter HyperRAMSize = 1024 * 1024
+  parameter HyperRAMClkFreq = 100_000_000,
+  parameter HyperRAMSize    = 1024 * 1024
 ) (
   input             clk_i,
   input             rst_ni,
@@ -31,7 +31,7 @@ module hyperram import tlul_pkg::*; #(
 );
 `ifdef USE_HYPERRAM_SIM_MODEL
   localparam int SRAMModelAddrWidth = $clog2(HyperRAMSize);
-  localparam int UnusedParams = HRClkFreq + HyperRAMSize;
+  localparam int UnusedParams = HyperRAMClkFreq + HyperRAMSize;
 
   tl_h2d_t unused_tl_b;
   assign unused_tl_b = '0;
@@ -73,7 +73,7 @@ module hyperram import tlul_pkg::*; #(
 
 `else
   hbmc_tl_top #(
-    .C_HBMC_CLOCK_HZ(HRClkFreq),
+    .C_HBMC_CLOCK_HZ(HyperRAMClkFreq),
     .C_HBMC_CS_MAX_LOW_TIME_US(4),
     .C_HBMC_FIXED_LATENCY(1'B0),
     .C_IDELAYCTRL_INTEGRATED(1'B0),

diff --git a/rtl/system/sonata_system.sv b/rtl/system/sonata_system.sv
@@ -8,11 +8,11 @@
 module sonata_system
   import sonata_pkg::*;
 #(
-  parameter int unsigned ArdAniWidth   = 6,
-  parameter int unsigned CheriErrWidth =  9,
-  parameter SRAMInitFile               = "",
-  parameter int unsigned SysClkFreq    = 30_000_000,
-  parameter int unsigned HRClkFreq     = 100_000_000
+  parameter int unsigned ArdAniWidth     = 6,
+  parameter int unsigned CheriErrWidth   =  9,
+  parameter SRAMInitFile                 = "",
+  parameter int unsigned SysClkFreq      = 30_000_000,
+  parameter int unsigned HyperRAMClkFreq = 100_000_000
 ) (
   // Main system clock and reset
   input logic                      clk_sys_i,
@@ -499,8 +499,8 @@ module sonata_system
   );
 
   hyperram #(
-    .HRClkFreq   (HRClkFreq),
-    .HyperRAMSize(HyperRAMSize)
+    .HyperRAMClkFreq ( HyperRAMClkFreq ),
+    .HyperRAMSize    ( HyperRAMSize    )
   ) u_hyperram (
     .clk_i  (clk_sys_i),
     .rst_ni (rst_sys_ni),