Skip to content

Commit

Permalink
HyperRAM permanently enabled
Browse files Browse the repository at this point in the history
SRAM is now fixed at 128 KiB

HyperRAM can no longer be disabled. This stops our memory map needing to
keep space for 256 KiB of SRAM even though our default configuration
only uses 128 KiB.

This commit also fixes the size of the revocation tags.
  • Loading branch information
marnovandermaas committed Nov 14, 2024
1 parent 2700cbb commit bcfdf6e
Show file tree
Hide file tree
Showing 12 changed files with 38 additions and 81 deletions.
4 changes: 2 additions & 2 deletions data/xbar_main.hjson
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@
xbar: false,
addr_range: [{
base_addr: "0x00100000",
size_byte: "0x00040000",
size_byte: "0x00020000",
}],
},
{ name: "hyperram", // HyperRAM memory
Expand All @@ -58,7 +58,7 @@
xbar: false,
addr_range: [{
base_addr: "0x30000000",
size_byte: "0x00004000",
size_byte: "0x00000800",
}],
},
{ name: "gpio", // General purpose input and output
Expand Down
4 changes: 2 additions & 2 deletions data/xbar_main_generated.hjson

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

2 changes: 1 addition & 1 deletion dv/verilator/sonata_system_main.cc
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ int main(int argc, char **argv) {
SonataSystem sonata_system(
"TOP.top_verilator.u_sonata_system.u_sram_top.u_ram.gen_generic.u_impl_generic",
32 * 1024, // 32k words = 128 KiB
"TOP.top_verilator.u_sonata_system.g_hyperram.u_hyperram.u_hyperram_model.u_ram.gen_generic.u_impl_generic",
"TOP.top_verilator.u_sonata_system.u_hyperram.u_hyperram_model.u_ram.gen_generic.u_impl_generic",
256 * 1024 // 256k words = 1 MiB
);

Expand Down
3 changes: 0 additions & 3 deletions dv/verilator/sonata_verilator_lint.vlt
Original file line number Diff line number Diff line change
Expand Up @@ -30,9 +30,6 @@ lint_off -rule UNOPTFLAT -file "*tlul_adapter_sram.sv" -match "*Signal unoptimiz
// to the error responder for the HyperRAM disabled config).
lint_off -rule UNOPTFLAT -file "*tlul_socket_m1.sv" -match "*Signal unoptimizable: Circular combinational logic: '*.u_hyperram_tl_socket.*'"

// False warning we're using 32-bit initial values for DisableHyperram parameter
lint_off -rule WIDTHTRUNC -file "*" -match "Operator VAR 'DisableHyperram' expects 1 bits on the Initial value*"

// Unimportant warning where compressed and uncompress instructions are printed in the same place.
lint_off -rule WIDTHEXPAND -file "*ibex_controller.sv" -match "*Conditional True's VARREF 'instr_compressed_i' generates 16 bits."

Expand Down
5 changes: 1 addition & 4 deletions dv/verilator/top_verilator.sv
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,6 @@
module top_verilator (input logic clk_i, rst_ni);
import sonata_pkg::*;

parameter bit DisableHyperram = 1'b0;

// System clock frequency.
localparam int unsigned SysClkFreq = 40_000_000;
// HyperRAM clock frequency.
Expand Down Expand Up @@ -301,8 +299,7 @@ module top_verilator (input logic clk_i, rst_ni);
sonata_system #(
.CheriErrWidth ( CheriErrWidth ),
.SysClkFreq ( SysClkFreq ),
.HRClkFreq ( HRClkFreq ),
.DisableHyperram ( DisableHyperram )
.HRClkFreq ( HRClkFreq )
) u_sonata_system (
// Main system clock and reset
.clk_sys_i (clk_i),
Expand Down
4 changes: 2 additions & 2 deletions rtl/bus/tl_main_pkg.sv

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

4 changes: 1 addition & 3 deletions rtl/fpga/top_sonata.sv
Original file line number Diff line number Diff line change
Expand Up @@ -206,7 +206,6 @@ module top_sonata
parameter int unsigned HRClkFreq = 100_000_000;

parameter SRAMInitFile = "";
parameter DisableHyperram = 1'b0;

// Main/board clock and reset
logic main_clk_buf;
Expand Down Expand Up @@ -270,8 +269,7 @@ module top_sonata
.CheriErrWidth ( 9 ),
.SRAMInitFile ( SRAMInitFile ),
.SysClkFreq ( SysClkFreq ),
.HRClkFreq ( HRClkFreq ),
.DisableHyperram ( DisableHyperram )
.HRClkFreq ( HRClkFreq )
) u_sonata_system (
// Main system clock and reset
.clk_sys_i (clk_sys),
Expand Down
79 changes: 26 additions & 53 deletions rtl/system/sonata_system.sv
Original file line number Diff line number Diff line change
Expand Up @@ -12,8 +12,7 @@ module sonata_system
parameter int unsigned CheriErrWidth = 9,
parameter SRAMInitFile = "",
parameter int unsigned SysClkFreq = 30_000_000,
parameter int unsigned HRClkFreq = 100_000_000,
parameter bit DisableHyperram = 1'b0
parameter int unsigned HRClkFreq = 100_000_000
) (
// Main system clock and reset
input logic clk_sys_i,
Expand Down Expand Up @@ -107,7 +106,7 @@ module sonata_system
// Signals, types and parameters for system. //
///////////////////////////////////////////////

localparam int unsigned MemSize = DisableHyperram ? 256 * 1024 : 128 * 1024; // 256 KiB
localparam int unsigned MemSize = 128 * 1024; // 128 KiB
localparam int unsigned SRAMAddrWidth = $clog2(MemSize);
localparam int unsigned HyperRAMSize = 1024 * 1024; // 1 MiB
localparam int unsigned DebugStart = 32'h1a110000;
Expand Down Expand Up @@ -499,54 +498,28 @@ module sonata_system
.tl_b_o (tl_sram_b_d2h)
);

if (DisableHyperram) begin : g_no_hyperram
logic unused_clk_hr;
logic unused_clk_hr90p;
logic unused_clk_hr3x;
logic unused_rst_hr;

assign unused_clk_hr = clk_hr_i;
assign unused_clk_hr90p = clk_hr90p_i;
assign unused_clk_hr3x = clk_hr3x_i;
assign unused_rst_hr = rst_hr_ni;

assign hyperram_dq = '0;
assign hyperram_rwds = '0;
assign hyperram_ckp = 1'b0;
assign hyperram_ckn = 1'b0;
assign hyperram_nrst = 1'b0;
assign hyperram_cs = 1'b0;

tlul_err_resp u_hyperram_err (
.clk_i (clk_sys_i),
.rst_ni (rst_sys_ni),
.tl_h_i(tl_hyperram_ds_h2d),
.tl_h_o(tl_hyperram_ds_d2h)
);
end else begin : g_hyperram
hyperram #(
.HRClkFreq (HRClkFreq),
.HyperRAMSize(HyperRAMSize)
) u_hyperram (
.clk_i (clk_sys_i),
.rst_ni (rst_sys_ni),

.clk_hr_i,
.clk_hr90p_i,
.clk_hr3x_i,
.rst_hr_ni,

.tl_i (tl_hyperram_ds_h2d),
.tl_o (tl_hyperram_ds_d2h),

.hyperram_dq,
.hyperram_rwds,
.hyperram_ckp,
.hyperram_ckn,
.hyperram_nrst,
.hyperram_cs
);
end
hyperram #(
.HRClkFreq (HRClkFreq),
.HyperRAMSize(HyperRAMSize)
) u_hyperram (
.clk_i (clk_sys_i),
.rst_ni (rst_sys_ni),

.clk_hr_i,
.clk_hr90p_i,
.clk_hr3x_i,
.rst_hr_ni,

.tl_i (tl_hyperram_ds_h2d),
.tl_o (tl_hyperram_ds_d2h),

.hyperram_dq,
.hyperram_rwds,
.hyperram_ckp,
.hyperram_ckn,
.hyperram_nrst,
.hyperram_cs
);

// Manual M:1 socket instantiation as xbar generator cannot deal with multiple ports for one
// device and we want to utilize the dual port SRAM. So totally separate crossbars are generated
Expand Down Expand Up @@ -668,8 +641,8 @@ module sonata_system
end
end

// Size of revocation tag memory is 4 KiB, one bit for each 64 in SRAM
localparam int unsigned RevTagDepth = 4 * 1024 * 8 / BusDataWidth;
// Size of revocation tag memory is one bit for each 64 in SRAM.
localparam int unsigned RevTagDepth = (MemSize / 8) / BusDataWidth;
localparam int unsigned RevTagAddrWidth = $clog2(RevTagDepth);

tlul_adapter_sram #(
Expand Down
8 changes: 0 additions & 8 deletions sonata.core
Original file line number Diff line number Diff line change
Expand Up @@ -89,11 +89,6 @@ parameters:
paramtype: vlogdefine
description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".

DisableHyperram:
datatype: bool
paramtype: vlogparam
description: Remove hyperram controller from the system (providing a larger SRAM)

USE_HYPERRAM_SIM_MODEL:
datatype: bool
paramtype: vlogdefine
Expand All @@ -118,7 +113,6 @@ targets:
parameters:
- SRAMInitFile
- PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
- DisableHyperram=false

sim:
<<: *default_target
Expand Down Expand Up @@ -146,7 +140,6 @@ targets:
- "--unroll-count 72"
parameters:
- PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
- DisableHyperram=false
- USE_HYPERRAM_SIM_MODEL=true

lint:
Expand All @@ -160,7 +153,6 @@ targets:
mode: lint-only
parameters:
- PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
- DisableHyperram=false
# TODO: Introduce some blackboxes for the Xilinx IP used in the hyperram
# controller so we can lint it, for now just exclude it from the lint run.
- USE_HYPERRAM_SIM_MODEL=true
2 changes: 1 addition & 1 deletion sw/cheri/boot/boot.S
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ start:
li a0, 0x30000000
csetaddr ca0, cs0, a0
li a1, 0
li a2, 4096
li a2, 2048
ccall bl_memset

// Set cgp to correct location so globals can be used.
Expand Down
2 changes: 1 addition & 1 deletion sw/cheri/checks/revocation_test.cc
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ using namespace CHERI;
uart.address() = UART_ADDRESS;
uart.bounds() = UART_BOUNDS;

unsigned int size_of_revocation_tags = 0x4000; // 16 KiB
unsigned int size_of_revocation_tags = 0x0800; // 2 KiB
unsigned int number_of_words = size_of_revocation_tags / 4;

Capability<volatile uint32_t> revocation_tags = root.cast<volatile uint32_t>();
Expand Down
2 changes: 1 addition & 1 deletion sw/cheri/common/boot.S
Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ start:
li a0, 0x30000000
csetaddr ca0, cs0, a0
li a1, 0
li a2, 4096
li a2, 2048
ccall bl_memset

// Set cgp to correct location so globals can be used.
Expand Down

0 comments on commit bcfdf6e

Please sign in to comment.