Updates for Xtensa enabled 1.83 compiler

.github/workflows/ci.yml

@@ -70,6 +70,7 @@ jobs:
       - uses: esp-rs/[email protected]
         with:
           ldproxy: false
+          version: 1.83.0.1
       # Install the Rust stable toolchain for RISC-V devices:
       - uses: dtolnay/rust-toolchain@v1
         with:

.github/workflows/documentation.yml

@@ -36,6 +36,7 @@ jobs:
         with:
           default: true
           ldproxy: false
+          version: 1.83.0.1
 
       - name: Checkout repository
         uses: actions/checkout@v4

.github/workflows/hil.yml

@@ -116,6 +116,7 @@ jobs:
           buildtargets: ${{ matrix.target.soc }}
           default: true
           ldproxy: false
+          version: 1.83.0.1
 
       - name: Build tests
         run: cargo xtask build-tests ${{ matrix.target.soc }}

esp-hal/src/analog/adc/esp32.rs

@@ -327,7 +327,7 @@ where
     }
 }
 
-impl<'d, ADC1> Adc<'d, ADC1> {
+impl<ADC1> Adc<'_, ADC1> {
     /// Enable the Hall sensor
     pub fn enable_hall_sensor() {
         unsafe { &*RTC_IO::ptr() }

esp-hal/src/assist_debug.rs

@@ -391,7 +391,7 @@ impl DebugAssist<'_> {
 }
 
 #[cfg(all(assist_debug_region_monitor, multi_core))]
-impl<'d> DebugAssist<'d> {
+impl DebugAssist<'_> {
     /// Enable region monitoring of read/write performed by the secondary CPU in
     /// a certain memory region0. Whenever the bus reads or writes in the
     /// specified memory region, an interrupt will be triggered.

esp-hal/src/dma/mod.rs

@@ -1892,7 +1892,7 @@ where
     }
 }
 
-impl<'a, M, CH> ChannelRx<'a, M, CH>
+impl<M, CH> ChannelRx<'_, M, CH>
 where
     M: Mode,
     CH: DmaRxChannel,
@@ -2186,7 +2186,7 @@ where
     }
 }
 
-impl<'a, M, CH> ChannelTx<'a, M, CH>
+impl<M, CH> ChannelTx<'_, M, CH>
 where
     M: Mode,
     CH: DmaTxChannel,

esp-hal/src/dma/pdma.rs

@@ -941,7 +941,7 @@ pub(super) fn init_dma(_cs: CriticalSection<'_>) {
     }
 }
 
-impl<'d, CH, M> Channel<'d, M, CH>
+impl<CH, M> Channel<'_, M, CH>
 where
     CH: DmaChannel,
     M: Mode,

esp-hal/src/gpio/mod.rs

@@ -2459,7 +2459,7 @@ mod asynch {
         pin: Flex<'d, P>,
     }
 
-    impl<'d, P: InputPin> PinFuture<'d, P> {
+    impl<P: InputPin> PinFuture<'_, P> {
         fn pin_mask(&self) -> u32 {
             let bank = self.pin.gpio_bank(private::Internal);
             1 << (self.pin.number() - bank.offset())

esp-hal/src/i2s/parallel.rs

@@ -401,7 +401,7 @@ where
     }
 }
 
-impl<'d, I, BUF, DM> Deref for I2sParallelTransfer<'d, BUF, DM, I>
+impl<I, BUF, DM> Deref for I2sParallelTransfer<'_, BUF, DM, I>
 where
     I: Instance,
     BUF: DmaTxBuffer,
@@ -414,7 +414,7 @@ where
     }
 }
 
-impl<'d, I, BUF, DM> DerefMut for I2sParallelTransfer<'d, BUF, DM, I>
+impl<I, BUF, DM> DerefMut for I2sParallelTransfer<'_, BUF, DM, I>
 where
     I: Instance,
     BUF: DmaTxBuffer,
@@ -425,7 +425,7 @@ where
     }
 }
 
-impl<'d, I, BUF, DM> Drop for I2sParallelTransfer<'d, BUF, DM, I>
+impl<I, BUF, DM> Drop for I2sParallelTransfer<'_, BUF, DM, I>
 where
     I: Instance,
     BUF: DmaTxBuffer,

esp-hal/src/lcd_cam/cam.rs

@@ -432,21 +432,21 @@ impl<'d, BUF: DmaRxBuffer> CameraTransfer<'d, BUF> {
     }
 }
 
-impl<'d, BUF: DmaRxBuffer> Deref for CameraTransfer<'d, BUF> {
+impl<BUF: DmaRxBuffer> Deref for CameraTransfer<'_, BUF> {
     type Target = BUF::View;
 
     fn deref(&self) -> &Self::Target {
         &self.buffer_view
     }
 }
 
-impl<'d, BUF: DmaRxBuffer> DerefMut for CameraTransfer<'d, BUF> {
+impl<BUF: DmaRxBuffer> DerefMut for CameraTransfer<'_, BUF> {
     fn deref_mut(&mut self) -> &mut Self::Target {
         &mut self.buffer_view
     }
 }
 
-impl<'d, BUF: DmaRxBuffer> Drop for CameraTransfer<'d, BUF> {
+impl<BUF: DmaRxBuffer> Drop for CameraTransfer<'_, BUF> {
     fn drop(&mut self) {
         self.stop_peripherals();
 

esp-hal/src/lcd_cam/lcd/dpi.rs

@@ -661,21 +661,21 @@ impl<'d, BUF: DmaTxBuffer, DM: Mode> DpiTransfer<'d, BUF, DM> {
     }
 }
 
-impl<'d, BUF: DmaTxBuffer, DM: Mode> Deref for DpiTransfer<'d, BUF, DM> {
+impl<BUF: DmaTxBuffer, DM: Mode> Deref for DpiTransfer<'_, BUF, DM> {
     type Target = BUF::View;
 
     fn deref(&self) -> &Self::Target {
         &self.buffer_view
     }
 }
 
-impl<'d, BUF: DmaTxBuffer, DM: Mode> DerefMut for DpiTransfer<'d, BUF, DM> {
+impl<BUF: DmaTxBuffer, DM: Mode> DerefMut for DpiTransfer<'_, BUF, DM> {
     fn deref_mut(&mut self) -> &mut Self::Target {
         &mut self.buffer_view
     }
 }
 
-impl<'d, BUF: DmaTxBuffer, DM: Mode> Drop for DpiTransfer<'d, BUF, DM> {
+impl<BUF: DmaTxBuffer, DM: Mode> Drop for DpiTransfer<'_, BUF, DM> {
     fn drop(&mut self) {
         self.stop_peripherals();
 

esp-hal/src/lcd_cam/lcd/i8080.rs

@@ -396,7 +396,7 @@ where
     }
 }
 
-impl<'d, DM: Mode> core::fmt::Debug for I8080<'d, DM> {
+impl<DM: Mode> core::fmt::Debug for I8080<'_, DM> {
     fn fmt(&self, f: &mut Formatter<'_>) -> core::fmt::Result {
         f.debug_struct("I8080").finish()
     }
@@ -470,15 +470,15 @@ impl<'d, BUF: DmaTxBuffer, DM: Mode> I8080Transfer<'d, BUF, DM> {
     }
 }
 
-impl<'d, BUF: DmaTxBuffer, DM: Mode> Deref for I8080Transfer<'d, BUF, DM> {
+impl<BUF: DmaTxBuffer, DM: Mode> Deref for I8080Transfer<'_, BUF, DM> {
     type Target = BUF::View;
 
     fn deref(&self) -> &Self::Target {
         &self.buf_view
     }
 }
 
-impl<'d, BUF: DmaTxBuffer, DM: Mode> DerefMut for I8080Transfer<'d, BUF, DM> {
+impl<BUF: DmaTxBuffer, DM: Mode> DerefMut for I8080Transfer<'_, BUF, DM> {
     fn deref_mut(&mut self) -> &mut Self::Target {
         &mut self.buf_view
     }
@@ -523,7 +523,7 @@ impl<'d, BUF: DmaTxBuffer> I8080Transfer<'d, BUF, crate::Async> {
     }
 }
 
-impl<'d, BUF: DmaTxBuffer, DM: Mode> Drop for I8080Transfer<'d, BUF, DM> {
+impl<BUF: DmaTxBuffer, DM: Mode> Drop for I8080Transfer<'_, BUF, DM> {
     fn drop(&mut self) {
         self.stop_peripherals();
 
@@ -645,7 +645,7 @@ impl<'d> TxEightBits<'d> {
     }
 }
 
-impl<'d> TxPins for TxEightBits<'d> {
+impl TxPins for TxEightBits<'_> {
     fn configure(&mut self) {
         const SIGNALS: [OutputSignal; 8] = [
             OutputSignal::LCD_DATA_0,
@@ -706,7 +706,7 @@ impl<'d> TxSixteenBits<'d> {
     }
 }
 
-impl<'d> TxPins for TxSixteenBits<'d> {
+impl TxPins for TxSixteenBits<'_> {
     fn configure(&mut self) {
         const SIGNALS: [OutputSignal; 16] = [
             OutputSignal::LCD_DATA_0,

esp-hal/src/ledc/timer.rs

@@ -369,7 +369,7 @@ impl TimerHW<LowSpeed> for Timer<'_, LowSpeed> {
 
 #[cfg(esp32)]
 /// Timer HW implementation for HighSpeed timers
-impl<'a> TimerHW<HighSpeed> for Timer<'a, HighSpeed> {
+impl TimerHW<HighSpeed> for Timer<'_, HighSpeed> {
     /// Get the current source timer frequency from the HW
     fn freq_hw(&self) -> Option<HertzU32> {
         self.clock_source.map(|source| match source {

esp-hal/src/otg_fs.rs

@@ -111,9 +111,9 @@ impl<'d> Usb<'d> {
     }
 }
 
-unsafe impl<'d> Sync for Usb<'d> {}
+unsafe impl Sync for Usb<'_> {}
 
-unsafe impl<'d> UsbPeripheral for Usb<'d> {
+unsafe impl UsbPeripheral for Usb<'_> {
     const REGISTERS: *const () = peripherals::USB0::ptr() as *const ();
 
     const HIGH_SPEED: bool = false;
@@ -250,7 +250,7 @@ pub mod asynch {
         inited: bool,
     }
 
-    impl<'d> Bus<'d> {
+    impl Bus<'_> {
         fn init(&mut self) {
             Usb::_enable();
 
@@ -336,7 +336,7 @@ pub mod asynch {
         }
     }
 
-    impl<'d> Drop for Bus<'d> {
+    impl Drop for Bus<'_> {
         fn drop(&mut self) {
             Bus::disable(self);
         }

esp-hal/src/rsa/esp32.rs

@@ -10,7 +10,7 @@ use crate::rsa::{
     RsaMultiplication,
 };
 
-impl<'d, DM: crate::Mode> Rsa<'d, DM> {
+impl<DM: crate::Mode> Rsa<'_, DM> {
     /// After the RSA Accelerator is released from reset, the memory blocks
     /// needs to be initialized, only after that peripheral should be used.
     /// This function would return without an error if the memory is initialized
@@ -79,7 +79,7 @@ pub mod operand_sizes {
     );
 }
 
-impl<'a, 'd, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularMultiplication<'a, 'd, T, DM>
+impl<'d, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularMultiplication<'_, 'd, T, DM>
 where
     T: RsaMode<InputType = [u32; N]>,
 {
@@ -98,7 +98,7 @@ where
     }
 }
 
-impl<'a, 'd, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularExponentiation<'a, 'd, T, DM>
+impl<'d, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularExponentiation<'_, 'd, T, DM>
 where
     T: RsaMode<InputType = [u32; N]>,
 {
@@ -108,7 +108,7 @@ where
     }
 }
 
-impl<'a, 'd, T: RsaMode + Multi, DM: crate::Mode, const N: usize> RsaMultiplication<'a, 'd, T, DM>
+impl<'d, T: RsaMode + Multi, DM: crate::Mode, const N: usize> RsaMultiplication<'_, 'd, T, DM>
 where
     T: RsaMode<InputType = [u32; N]>,
 {

esp-hal/src/rsa/esp32sX.rs

@@ -10,7 +10,7 @@ use crate::rsa::{
     RsaMultiplication,
 };
 
-impl<'d, DM: crate::Mode> Rsa<'d, DM> {
+impl<DM: crate::Mode> Rsa<'_, DM> {
     /// After the RSA accelerator is released from reset, the memory blocks
     /// needs to be initialized, only after that peripheral should be used.
     /// This function would return without an error if the memory is
@@ -248,7 +248,7 @@ pub mod operand_sizes {
     );
 }
 
-impl<'a, 'd, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularExponentiation<'a, 'd, T, DM>
+impl<'d, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularExponentiation<'_, 'd, T, DM>
 where
     T: RsaMode<InputType = [u32; N]>,
 {
@@ -268,7 +268,7 @@ where
     }
 }
 
-impl<'a, 'd, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularMultiplication<'a, 'd, T, DM>
+impl<'d, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularMultiplication<'_, 'd, T, DM>
 where
     T: RsaMode<InputType = [u32; N]>,
 {
@@ -281,7 +281,7 @@ where
     }
 }
 
-impl<'a, 'd, T: RsaMode + Multi, DM: crate::Mode, const N: usize> RsaMultiplication<'a, 'd, T, DM>
+impl<'d, T: RsaMode + Multi, DM: crate::Mode, const N: usize> RsaMultiplication<'_, 'd, T, DM>
 where
     T: RsaMode<InputType = [u32; N]>,
 {

esp-hal/src/rtc_cntl/sleep/esp32s3.rs

@@ -234,7 +234,7 @@ impl Drop for Ext1WakeupSource<'_, '_> {
     }
 }
 
-impl<'a, 'b> RtcioWakeupSource<'a, 'b> {
+impl RtcioWakeupSource<'_, '_> {
     fn apply_pin(&self, pin: &mut dyn RtcPin, level: WakeupLevel) {
         let rtcio = unsafe { &*crate::peripherals::RTC_IO::PTR };
 

esp-hal/src/soc/esp32/cpu_control.rs

@@ -127,7 +127,7 @@ pub struct AppCoreGuard<'a> {
     phantom: PhantomData<&'a ()>,
 }
 
-impl<'a> Drop for AppCoreGuard<'a> {
+impl Drop for AppCoreGuard<'_> {
     fn drop(&mut self) {
         unsafe {
             internal_park_core(Cpu::AppCpu);
@@ -323,6 +323,7 @@ impl<'d> CpuControl<'d> {
     where
         F: FnOnce(),
     {
+        #[allow(static_mut_refs)] // FIXME
         match START_CORE1_FUNCTION.take() {
             Some(entry) => {
                 let entry = unsafe { ManuallyDrop::take(&mut *entry.cast::<ManuallyDrop<F>>()) };

esp-hal/src/soc/esp32s3/cpu_control.rs

@@ -127,7 +127,7 @@ pub struct AppCoreGuard<'a> {
     phantom: PhantomData<&'a ()>,
 }
 
-impl<'a> Drop for AppCoreGuard<'a> {
+impl Drop for AppCoreGuard<'_> {
     fn drop(&mut self) {
         unsafe {
             internal_park_core(Cpu::AppCpu);
@@ -259,6 +259,7 @@ impl<'d> CpuControl<'d> {
     where
         F: FnOnce(),
     {
+        #[allow(static_mut_refs)] // FIXME
         match START_CORE1_FUNCTION.take() {
             Some(entry) => {
                 let entry = unsafe { ManuallyDrop::take(&mut *entry.cast::<ManuallyDrop<F>>()) };

esp-hal/src/soc/mod.rs

@@ -30,6 +30,7 @@ static mut MAPPED_PSRAM: MappedPsram = MappedPsram { memory_range: 0..0 };
 pub(crate) fn psram_range() -> Range<usize> {
     cfg_if::cfg_if! {
         if #[cfg(any(feature = "quad-psram", feature = "octal-psram"))] {
+            #[allow(static_mut_refs)]
             unsafe { MAPPED_PSRAM.memory_range.clone() }
         } else {
             0..0

esp-hal/src/spi/slave.rs

@@ -315,7 +315,7 @@ pub mod dma {
         }
     }
 
-    impl<'d, M, T> SpiDma<'d, M, T>
+    impl<M, T> SpiDma<'_, M, T>
     where
         M: Mode,
         T: InstanceDma,