Simulator compatibility

manifest

@@ -1,47 +1,47 @@
-d328f88dd48e015bbaa95e0d7c88954343cc5632  verilog/rtl/DFFRAM.v
-dab57f3c5464ce3354219840dae589a3fcd27135  verilog/rtl/DFFRAMBB.v
+e80d15d008cf6a03a44bba3be5002e32a6effc16  verilog/rtl/DFFRAM.v
+5c35006cfe9fe7c583f5bb6809afdeb2ef527e2d  verilog/rtl/DFFRAMBB.v
 535d0592c0b1349489b6b86fd5449f9d1d81482e  verilog/rtl/__uprj_analog_netlists.v
 87735eb5981740ca4d4b48e6b0321c8bb0023800  verilog/rtl/__uprj_netlists.v
-ef9cf827273c2a245f807725f33bb3bc6e51ba54  verilog/rtl/__user_analog_project_wrapper.v
-c3616f10b8d437432a30dc0dbf2235d50c4f5847  verilog/rtl/__user_project_wrapper.v
-6229bc5cbbe404575340153b4274033ca8d66c38  verilog/rtl/caravan.v
+144fd2bcd269472374fa3ae6162a57f7835871a9  verilog/rtl/__user_analog_project_wrapper.v
+1f83da79ede7775e3b0d3b1c078123a22dc1b94c  verilog/rtl/__user_project_wrapper.v
+3ee8c61791ee73810263d93631e9ee0736012964  verilog/rtl/caravan.v
 31775f9c43c80b137a1cbbc9dd78e4e96708a8e9  verilog/rtl/caravan_netlists.v
-6ff514c11754375cd9c86229d4466c071617e8c2  verilog/rtl/caravel.v
-b2feeb2a098894d5d731a5b011858a471e855d73  verilog/rtl/caravel_clocking.v
-7c4b2a8c1a70bbf13291f25973a4f776c804909e  verilog/rtl/chip_io.v
-a6f9dbe63659a716d85f646b14421b9ad0425186  verilog/rtl/chip_io_alt.v
-d772308bd2a72121d7ed9dcdd40c8e6cbbe4b43c  verilog/rtl/clock_div.v
-f937b52e53d45bdbe41bcbd07c65b41104c21756  verilog/rtl/convert_gpio_sigs.v
-21204dc96bdb3c1295dd06375293ee3d811d2f7e  verilog/rtl/counter_timer_high.v
-6b9b2ab85a85f73d6ce686c67fc85e59d9623ee6  verilog/rtl/counter_timer_low.v
-fff2d08e49701312c2ebd6714b7425baf83f3d35  verilog/rtl/digital_pll.v
-ce49f9af199b5f16d2c39c417d58e5890bc7bab2  verilog/rtl/digital_pll_controller.v
-89dee515f5819e4f5d572f9542ca19798f4b6c4e  verilog/rtl/gpio_control_block.v
-57554b3586f306944b31718a8c52526fa9a8a574  verilog/rtl/gpio_wb.v
-baf3aba29655ca7021398ddc3f68be81eff0fa0c  verilog/rtl/housekeeping_spi.v
-6c11ee92e0b2995982041d8a599b5d46b7dde838  verilog/rtl/la_wb.v
-ff3e65a783f3807340e25efac9207787d39fb6cd  verilog/rtl/mem_wb.v
-0894819fdfdcc1cb7a0fcacca3ac133f9884cc5a  verilog/rtl/mgmt_core.v
-65934e08f3ad2d5fbacd8fc68eae0bb485c25309  verilog/rtl/mgmt_protect.v
-3b1ff20593bc386d13f5e2cf1571f08121889957  verilog/rtl/mgmt_protect_hv.v
-85bc308843b6aad96ac9e75f49c942db8e1c0afe  verilog/rtl/mgmt_soc.v
+fc02a1dd5fddef63591e5aa34bb46c6277c5950b  verilog/rtl/caravel.v
+d8995a9f8cc795b3e8c677166a93c5fd8914d4ab  verilog/rtl/caravel_clocking.v
+a6c35338687c0249898a290c2cc606da3cf4e165  verilog/rtl/chip_io.v
+75d65f67819956159f6cc112a6eb026030269878  verilog/rtl/chip_io_alt.v
+980608198b184e9eab4787c7418626225be1ce91  verilog/rtl/clock_div.v
+bcf4a2476054e72aa4bea78a9d5032849e9568d0  verilog/rtl/convert_gpio_sigs.v
+044c59316aac36d11da8be2c9243b239bb097b02  verilog/rtl/counter_timer_high.v
+6c9e2c65cebd65c77a5ddf2b81fd17781e5ab744  verilog/rtl/counter_timer_low.v
+fa8bd588477f9ad8b63c27eb81cb7623ba449ca4  verilog/rtl/digital_pll.v
+284d191f252dcfbdb03431f2cf0196fb4b969173  verilog/rtl/digital_pll_controller.v
+df03577698eeca10cb4e14dc8ef052d3df9f7378  verilog/rtl/gpio_control_block.v
+325dd37baeab4c05ada86573a894d5d8a4e5da82  verilog/rtl/gpio_wb.v
+1f7ff151c206c41fe5c39d13138b4303aa8dd0a8  verilog/rtl/housekeeping_spi.v
+c6fe30f47b6948c7d13e8e9bced245ed64a17179  verilog/rtl/la_wb.v
+de8921ac6a86f18ad14feb017cfbbc23657f2870  verilog/rtl/mem_wb.v
+ad03a871a8271dfd00564a6acba0ae0b37c325ef  verilog/rtl/mgmt_core.v
+fdf6bbb948ca3386bc81369fc94aff7745fa3637  verilog/rtl/mgmt_protect.v
+93903f794edd129825fe6bbde271bd06baae2ade  verilog/rtl/mgmt_protect_hv.v
+aa21d0aed7f9ef1ac39e56f8f34f336fbee10d4b  verilog/rtl/mgmt_soc.v
 9816acedf3dc3edd193861cc217ec46180ac1cdd  verilog/rtl/mprj2_logic_high.v
-b4395fbd17108e58e33a620159464ae944a15878  verilog/rtl/mprj_ctrl.v
-a61f5566f5d369d879c47d6b65f99cf297debe8f  verilog/rtl/mprj_io.v
+8e2fe315a8d3ab4148782478932c2f7491fef20d  verilog/rtl/mprj_ctrl.v
+86f2596c83b7df0b054d80dce1b33751f9d9ff50  verilog/rtl/mprj_io.v
 b928ab6205a267f6ac83c603965c6f34a486724e  verilog/rtl/mprj_logic_high.v
-eac1e6d413cdfbc2f802e229ae5058828e01be1e  verilog/rtl/pads.v
-b5aff2fda5078cfda377b98337fcc91040815fc2  verilog/rtl/picorv32.v
-669d16642d5dd5f6824812754db20db98c9fe17b  verilog/rtl/ring_osc2x13.v
-6864cc10dacfd3edb4c66825b7a301ab097cea0d  verilog/rtl/simple_por.v
-917aa6e1bb869f973c79fb2c7894eab882ead74c  verilog/rtl/simple_spi_master.v
-d43221ffa0f2d760991d8b911b4a5292911203f5  verilog/rtl/simpleuart.v
+de677b27ae74fdf2674ceb70df062f90582d4fe6  verilog/rtl/pads.v
+f297c3b729e92baae4f9cf90177278a93cb1f44e  verilog/rtl/picorv32.v
+2668c372527e6879920da9e930d6a1cd44f68fe6  verilog/rtl/ring_osc2x13.v
+b4ee56a9c1999b97a6ad58f0ad98d0e751c85e20  verilog/rtl/simple_por.v
+f46abcc049b7d4a16b331854deee3768483292d0  verilog/rtl/simple_spi_master.v
+fea2533928785182e2ae9ea9d5d47a84b0f25843  verilog/rtl/simpleuart.v
 46bca62460c4dbfac30233318b24c3d526a40058  verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
-eb0c856ab69e8c364c04bdc149db9d82ae67b39d  verilog/rtl/spimemio.v
-3b4c3de623f8af0f0780f1e5b0f2217ef6406a2f  verilog/rtl/sram_1rw1r_32_256_8_sky130.v
-da42d868bfe847b83ed0a3e6e8307216a6f3fa21  verilog/rtl/storage.v
-7e8d789570ed224df49cf61f69593cc738790a5d  verilog/rtl/storage_bridge_wb.v
-5e314e94a13d7291117123395ae088e1d17cf487  verilog/rtl/sysctrl.v
-e6246df6bbf0860a331b3547d64f7d235b0eca9a  verilog/rtl/wb_intercon.v
+3d945b85b5c2d8f1d2eff8d9a189cd1d3a5584f3  verilog/rtl/spimemio.v
+6b55019e80874ccbd43ec3d559499c328eb385d7  verilog/rtl/sram_1rw1r_32_256_8_sky130.v
+4557c05867ca42c3de4f4cd35c1c3195d6b3886f  verilog/rtl/storage.v
+42e604a40a787d25e839664c117c0b7317dd73d5  verilog/rtl/storage_bridge_wb.v
+db70a9a4a296376ae79c3e46bd26985ca6c54f18  verilog/rtl/sysctrl.v
+db9739e72cc1a5c1cd624f0ba3a54b6348ad2a00  verilog/rtl/wb_intercon.v
 9d06bd68e8ec6918cd3ef5467cb8cee44e7e3a26  scripts/set_user_id.py
 be50a23e39bf13eed5090ac819b785afdba587b0  scripts/generate_fill.py
 e3793327393803e44a90a702c5413facbb4b46e8  scripts/compositor.py

verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v

@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -211,4 +210,3 @@ module caravan_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v

@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -193,4 +192,3 @@ module gpio_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*	
 	StriVe housekeeping SPI testbench.
 */
@@ -428,4 +427,3 @@ module hkspi_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/mem/mem_tb.v

@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -200,4 +199,3 @@ module mem_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
@@ -173,4 +172,3 @@ module mprj_ctrl_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*	
  *	StriVe housekeeping pass-thru mode SPI testbench.
  */
@@ -347,4 +346,3 @@ module pass_thru_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/perf/perf_tb.v

@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -156,4 +155,3 @@ module perf_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/pll/pll_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
@@ -155,4 +154,3 @@ module pll_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v

@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -202,4 +201,3 @@ module qspi_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/storage/storage_tb.v

@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -187,4 +186,3 @@ module storage_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
@@ -217,4 +216,3 @@ module sysctrl_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/timer/timer_tb.v

@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -198,4 +197,3 @@ module timer_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v

@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -226,4 +225,3 @@ module timer2_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/mgmt_soc/uart/uart_tb.v

@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -147,4 +146,3 @@ module uart_tb;
 	);
 
 endmodule
-`default_nettype wire

verilog/dv/caravel/spiflash.v

@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017 Clifford Wolf
  *

verilog/dv/caravel/tbuart.v

@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017 Clifford Wolf
  *

verilog/dv/dummy_slave.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module dummy_slave(
     input wb_clk_i,
     input wb_rst_i,

verilog/dv/wb_utests/chip_io/chip_io_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 

verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

verilog/dv/wb_utests/la_wb/la_wb_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 `timescale 1 ns / 1 ps
 
 `include "la_wb.v"

verilog/dv/wb_utests/mem_wb/mem_wb_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

verilog/dv/wb_utests/storage_wb/storage_wb_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // `define DBG
 
 `define STORAGE_BASE_ADR  32'h0100_0000

verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 

verilog/dv/wb_utests/uart_wb/uart_wb_tb.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps

verilog/gl/__user_project_wrapper.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
  *-------------------------------------------------------------
  *

verilog/gl/gpio_control_block.v

@@ -1,4 +1,3 @@
-`default_nettype wire
 module gpio_control_block (mgmt_gpio_in,
     mgmt_gpio_oeb,
     mgmt_gpio_out,

verilog/gl/storage.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module storage(mgmt_clk, mgmt_ena_ro, VPWR, VGND, mgmt_addr, mgmt_addr_ro, mgmt_ena, mgmt_rdata, mgmt_rdata_ro, mgmt_wdata, mgmt_wen, mgmt_wen_mask);

verilog/rtl/DFFRAM.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 `ifndef USE_CUSTOM_DFFRAM
 
 module DFFRAM(

verilog/rtl/DFFRAMBB.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
     Building blocks for DFF based RAM compiler for SKY130A 
     BYTE        :   8 memory cells used as a building block for WORD module

verilog/rtl/__user_analog_project_wrapper.v

@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
  *-------------------------------------------------------------
  *