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Simulator compatibility #57

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Simulator compatibility #57

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Commits on May 5, 2021

  1. Use Verilog-2001 Port declaration only 

    Most files use the Verilog-2001 port declaration style using implicit type declaration.
In cases where the port type must be changed, e.g. an output as reg, it was set in the body of the module (a là Verilog-1995), instead of the header after the direction specification.
E.g. in user_id_programming.v:
```
module user_id_programming #(
    ..-
) (
    output [31:0] mask_rev
);

    wire [31:0] mask_rev;
    wire [31:0] user_proj_id_high;
    wire [31:0] user_proj_id_low;
    ....
endmodule
```

This seems to be a problem for some simulators, e.g. Modelsim, which think the `wire [31:0] mask_rev;` line declares a new wire. because the name was already used in the scope this results in an error.
Thus such cases where made to use the 2001-style port declaration only.
    @heavySea
    heavySea committed May 5, 2021
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  2. Exclude substrate ground connections for Simulation 

    Solves efabless/caravel#54
    @heavySea
    heavySea committed May 5, 2021
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  3. Suggested Fix for efabless/caravel#55 

    Remove the compiler directives related to default port type
    @heavySea
    heavySea committed May 5, 2021
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  4. Update manifest

    @heavySea
    heavySea committed May 5, 2021
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