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Feature: RISC-V System Bus support #1683

Merged
merged 17 commits into from
Nov 14, 2023
Merged

Feature: RISC-V System Bus support #1683

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88be0fa
riscv_debug: Too wide a CSR access triggers a not-supported error on …
dragonmux Feb 13, 2023
b8806a1
riscv_debug: Implemented DMI sticky error recovery
dragonmux Feb 13, 2023
e1546bc
riscv_jtag_dtm: Fixed riscv_shift_dmi() not implementing handling for…
dragonmux Mar 28, 2023
f260dec
riscv_jtag_dtm: Adjusted riscv_jtag_dmi_write() with handling for RV_…
dragonmux Mar 28, 2023
30ce4c5
riscv_debug: Added in some additional protocol-level logging in the D…
dragonmux Mar 28, 2023
1bfaf85
riscv32: Refactored the memory access routines to allow a target to s…
dragonmux Mar 28, 2023
8066f0d
riscv32: Implemented protocol-level debug diagnostics for memory reads
dragonmux Nov 10, 2023
cf1db10
riscv32: Implemented protocol-level debug diagnostics for memory writes
dragonmux Nov 10, 2023
08c252e
riscv_debug: Implemented support for detecting and switching over to …
dragonmux Mar 28, 2023
078c966
riscv_debug: Naming cleanup of the constants involved in abstract com…
dragonmux Mar 28, 2023
de04cbb
riscv32: Implemented memory read via system bus
dragonmux Mar 28, 2023
198ffd5
riscv32: Implemented memory write via sytem bus
dragonmux Mar 28, 2023
f7cc0a5
riscv32: Refactored out the native-width system bus access logic into…
dragonmux Mar 29, 2023
2387394
riscv32: Implemented support for non-native-width system bus memory r…
dragonmux Mar 29, 2023
a55e800
riscv32: Refactored out the native-width system bus write logic into …
dragonmux Apr 1, 2023
747b6f9
riscv32: Implemented support for non-native-width system bus memory w…
dragonmux Apr 1, 2023
9b200e7
riscv32: Fixed a typo in one of the comments in `riscv32_abstract_mem…
dragonmux Nov 10, 2023
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