Feature: RISC-V System Bus support

[dragonmux]

Detailed description

In this PR we implement support for the RISC-V debug 'System Bus' (sysbus) component, as not all targets have to nor do implement the memory I/O abstract command. This complicates things but is required to support, eg, the ESP32-C3.

To accomplish this, we have to deal with sysbus having made all I/O widths optional to support while also needing to be able to do any arbitrarily sized and aligned read/write. The one benefit is that, depending on implementation, sysbus may be used without halting the Hart, unlike the abstract command interface which requires it halted (read: due to it injecting an instruction stream into the core to run the read/write, though this is strictly an implementation detail).

Unfortunately, this puts the burden of performing the I/O correctly on us, but we've attempted to minimise the logic and complications caused by this and document everything thoroughly. This logic has been tested on an ESP32-C3 and works.

Your checklist for this pull request

• I've read the Code of Conduct
• I've read the guidelines for contributing to this repository
• It builds for hardware native (make PROBE_HOST=native)
• It builds as BMDA (make PROBE_HOST=hosted)
• I've tested it to the best of my ability
• My commit messages provide a useful short description of what the commits do

Closing issues

[esden]

LGTM