Feature: Cortex-R support

src/Makefile

@@ -1,7 +1,8 @@
 PROBE_HOST ?= native
 PLATFORM_DIR = platforms/$(PROBE_HOST)
 VPATH += $(PLATFORM_DIR) target
-ENABLE_DEBUG ?=
+ENABLE_DEBUG ?= 0
+ENABLE_CORTEXR ?= 0
 
 SYS = $(shell $(CC) -dumpmachine)
 
@@ -89,6 +90,11 @@ ifeq (,$(filter all_platforms,$(MAKECMDGOALS)))
 include $(PLATFORM_DIR)/Makefile.inc
 endif
 
+ifeq ($(ENABLE_CORTEXR), 1)
+CFLAGS += -DENABLE_CORTEXR
+SRC += cortexr.c
+endif
+
 ifneq ($(PC_HOSTED),1)
 # Output memory usage information
 LDFLAGS += -Wl,--print-memory-usage

src/platforms/hosted/Makefile.inc

@@ -5,6 +5,8 @@ SYS := $(shell $(CC) -dumpmachine)
 CFLAGS += -DENABLE_DEBUG -DPLATFORM_HAS_DEBUG
 CFLAGS +=-I ./target
 
+ENABLE_CORTEXR := 1
+
 # Clang requires some special handling here: -gnu means MinGW
 # while -msvc means Clang/CL. We don't currently support the latter
 # and we need the former to fit the formula of `x86_64-w64-mingw32`

src/target/adiv5.c

@@ -122,6 +122,7 @@ typedef enum arm_arch {
 	aa_nosupport,
 	aa_cortexm,
 	aa_cortexa,
+	aa_cortexr,
 	aa_end
 } arm_arch_e;
 
@@ -243,7 +244,7 @@ static const struct {
 	{0xc08, 0x00, 0, aa_cortexa, cidc_dc, ARM_COMPONENT_STR("Cortex-A8 Debug", "(Debug Unit)")},
 	{0xc09, 0x00, 0, aa_cortexa, cidc_dc, ARM_COMPONENT_STR("Cortex-A9 Debug", "(Debug Unit)")},
 	{0xc0f, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-A15 Debug", "(Debug Unit)")}, /* support? */
-	{0xc14, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Cortex-R4 Debug", "(Debug Unit)")},  /* support? */
+	{0xc14, 0x15, 0, aa_cortexr, cidc_unknown, ARM_COMPONENT_STR("Cortex-R4", "(Debug Unit)")},
 	{0xcd0, 0x00, 0, aa_nosupport, cidc_unknown, ARM_COMPONENT_STR("Atmel DSU", "(Device Service Unit)")},
 	{0xd20, 0x00, 0x2a04, aa_cortexm, cidc_gipc, ARM_COMPONENT_STR("Cortex-M23", "(System Control Space)")},
 	{0xd20, 0x11, 0, aa_nosupport, cidc_dc, ARM_COMPONENT_STR("Cortex-M23", "(Trace Port Interface Unit)")},
@@ -687,6 +688,10 @@ static void adiv5_component_probe(
 				DEBUG_INFO("%s-> cortexa_probe\n", indent + 1);
 				cortexa_probe(ap, addr);
 				break;
+			case aa_cortexr:
+				DEBUG_INFO("%s-> cortexr_probe\n", indent + 1);
+				cortexr_probe(ap, addr);
+				break;
 			default:
 				break;
 			}

src/target/cortex.c

@@ -101,6 +101,12 @@ void cortex_read_cpuid(target_s *target)
 	case CORTEX_A9:
 		target->core = "A9";
 		break;
+	case CORTEX_R4:
+		target->core = "R4";
+		break;
+	case CORTEX_R5:
+		target->core = "R5";
+		break;
 	case STAR_MC1:
 		target->core = "STAR-MC1";
 		break;

src/target/cortex.h

@@ -50,6 +50,10 @@
 #define CORTEX_M33 0xd210U
 #define STAR_MC1   0x1320U
 
+/* Cortex-R CPU IDs */
+#define CORTEX_R4 0xc140U
+#define CORTEX_R5 0xc150U
+
 /* Cortex-A CPU IDs */
 #define CORTEX_A5 0xc050U
 #define CORTEX_A7 0xc070U
@@ -65,6 +69,7 @@
 #define CORTEX_REG_MSP     17U
 #define CORTEX_REG_PSP     18U
 #define CORTEX_REG_SPECIAL 19U
+#define CORTEX_REG_FPCSR   49U
 
 #define CORTEX_CPUID_PARTNO_MASK   0xfff0U
 #define CORTEX_CPUID_REVISION_MASK 0x00f00000U