Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Updates #105

Open
wants to merge 30 commits into
base: main
Choose a base branch
from
Open
Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
30 commits
Select commit Hold shift + click to select a range
8c94418
Don't keep generated 7020 bitstream in version control.
olajep Dec 5, 2016
c0a4e47
Add parallella_base intermediate files to gitignore
olajep Dec 5, 2016
f3e7c53
parallella/fpga: Set CFG_PLATFORM to "ZYNQ"
olajep May 19, 2019
1f439c0
common: oh_mux: Fix Vivado issues
olajep May 21, 2019
102b293
elink: Fix I/O primitives for Zynq
olajep May 21, 2019
a2e31d6
parallella/fpga: Regenerate block design scripts
olajep May 21, 2019
1be6358
xilibs: Upgrade IPs to Vivado 2018.2
olajep May 21, 2019
b2d93da
parallella/fpga: Fix Makefile clean target
olajep May 25, 2019
8413afd
Don't keep generated 7020 bitstream in version control
olajep May 25, 2019
e3f19ed
parallella/fpga: Use offset 0 over 8 for hdmi_d pins
olajep May 26, 2019
339e662
parallella/fpga: Add hdmi_e16_z7020 project
olajep May 26, 2019
00fa7f8
ip: fifo_async_104x32: Use GLOBAL synthesis flow
olajep May 26, 2019
86e4eba
parallella/fpga: Use same net names across block designs
olajep May 26, 2019
b3785c4
adi: Import ADI HDL IP:s needed by HDMI designs
olajep May 26, 2019
d9856f5
adi: Add Makefile
olajep May 26, 2019
100a825
parallella/fpga: Makefile: Build ADI ips
olajep May 26, 2019
b2e964d
parallella/fpga: Use in-tree ADI IP repo
olajep May 26, 2019
9a8ad92
parallella/fpga: hdmi: Fix too long net name warnings
olajep May 26, 2019
a69142d
parallella/fpga: Add hdmi_e16_z7010 project
olajep May 26, 2019
4be69a2
adi: hdl: Import axi_dmac IP
olajep May 26, 2019
d8f88cd
adi: hdl: Add dependencies needed by axi_dmac
olajep May 26, 2019
e6b71be
adi: hdl: Add xi_dmac IP to Makefile
olajep May 26, 2019
419fdf2
parallella/fpga: hdmi: Mimic ADI reference design
olajep May 26, 2019
20b54a2
parallella/fpga: hdmi z7010: Try fixing clock implementation error
olajep May 27, 2019
6a61271
oh_memory_ram: Use LUTs over BRAM on ZYNQ
olajep May 27, 2019
e7da362
parallella/fgpa: HDMI: Use same SPDIF clock config for z7010 and z7020
olajep May 27, 2019
b57c799
parallella/fpga: HDMI: Minor visual block design improvements
olajep May 27, 2019
c964034
parallella/fpga: Fix typo in Makefile clean target
olajep May 27, 2019
a50cdb7
parallella/fpga: parallella_base Add more files to clean target
olajep May 27, 2019
9e60a0c
parallella/fpga: Fix timing warning
olajep May 28, 2019
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 2 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -54,3 +54,5 @@ xgui/
#ASIC proprietary files
proprietary/

# parallella_base intermediate files
src/parallella/fpga/parallella_base/src
14 changes: 14 additions & 0 deletions src/adi/Makefile
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
LIBRARY := ./hdl/library
IPS := axi_clkgen axi_hdmi_tx axi_spdif_tx axi_dmac

.PHONY: all clean

all:
for ip in $(IPS); do \
make -C $(LIBRARY)/$$ip; \
done

clean:
for ip in $(IPS); do \
make -C $(LIBRARY)/$$ip clean; \
done
15 changes: 15 additions & 0 deletions src/adi/hdl/.gitattributes
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
* text=auto

*.c text
*.h text
*.prj
*.tcl text
*.txt text
*.ucf text
*.v text
*.vhd text
*.xdc text
*.xml text
*.qsys text
*.xise text
Makefile text
79 changes: 79 additions & 0 deletions src/adi/hdl/.gitignore
Original file line number Diff line number Diff line change
@@ -0,0 +1,79 @@
*.cache
*.data
*.xpr
*.log
*.bld
*.chk
*.cmd_log
*.cxt
*.gise
*.gyd
*.jed
*.lso
*.mfd
*.nga
*.ngc
*.ngd
*.ngr
*.pad
*.pnx
*.prj
*.rpt
*.stx
*.syr
*.tim
*.tspec
*.vm6
*.xst
*.html
*.xrpt
*.err
*_html
*.sld
*.txt
*.qsys
*.csv
xst
netgen
iseconfig
xlnx_auto*
_ngo
_xmsgs
component.xml
*.jou
xgui
*.runs
*.srcs
*.sdk
.Xil
*_INFO.txt
*_dump.txt
db
*.asm.rpt
*.done
*.eda.rpt
*.fit.*
*.map.*
*.sta.*
*.qsf
*.qpf
*.qws
*.sof
*.rbf
system_qsys_script.tcl
hc_output
hps_isw_handoff
hps_sdram_*.csv
incremental_db
system_bd/
reconfig_mif
*.sopcinfo
*.jdi
*.pin
*.os
*webtalk*
*.xml
*.hw
gui
.timestamp_altera

57 changes: 57 additions & 0 deletions src/adi/hdl/LICENSE
Original file line number Diff line number Diff line change
@@ -0,0 +1,57 @@

In this HDL repository, there are many different and unique modules, consisting
of various HDL (Verilog or VHDL) components. The individual modules are
developed independently, and may be accompanied by separate and unique license
terms (such as GPL, LGPL, BSD, modified BSD, commercial or others). Your license
rights with respect to individual modules accompanied by separate license terms
are defined by those terms. The license agreement for each module is generally
located in the module source code. Nothing else shall restrict, limit, or
otherwise affect any rights or obligations you may have, or conditions to which
you may be subject, under such license terms. This agreement does not limit your
rights under, or grant you rights that supersede, the license terms of any
particular module.

The mere aggregation of these modules (putting them side by side in the same
source code repository or on a hard disk) does not mean that there is one master
license for all the files. It is up to you, the user, to ensure that during the
building a project, which combines these modules together so that they form a
bit file (either one, or multiple for partial reconfiguration), all the individual
licenses are compatible. For example, if a single module is covered by the GPL,
the whole combination must also be released under the GPL. If you can't, or
won't, do that, you may not distribute the resulting bit file.

The majority of ADI created modules are dual-licensed, allowing the user to pick
which license they want to use, (and the rights and obligations they have).
- The ADI BSD license, which allows you to make bit files, and not release your
source, as long as it attaches to an ADI device. This is not truly open
source, since it does place extra restrictions on developers.
- The GPL v2 license, which allows you to make bit files, but you must release
all other HDL (except vendor produced, which we consider as a run-time library),
permitted by GPL section 3, along with your bit file. This is truly open
source, and places no additional restrictions on use or fields of endeavor. The
GPL is ideal for use cases such as open source projects with open source
distribution, student/academic purposes, hobby projects, internal research
projects without external distribution, or other projects where all GPL
obligations can be met.

In these cases, support is handled via web (https://ez.analog.com/community/fpga),
on a best effort basis. Note that our best efforts may not match your product
development schedule. This is a free, non-deterministic support, and is not meant
as a replacement for professional services. However, if this is not adequate
for your needs, or you require support within a specific time frame we recommend
you seek alternatives including seeking professional service and/or commercial/deterministic
support.

There are also specific modules which are only single-licensed, as listed
below. This list may not be complete, it's up to the user to check each module
license.
- SPDIF, which is released under the LGPL license only. See
https://opencores.org/project,spdif_interface for support.
- The ADI created JESD Core, which is released under the GPL and a commercial
license only.
+ The commercial license gives you the full rights to create and distribute
bit files on your own terms without any open source license obligations,
and special avenues for support may be possible. If you are interested
in such a license, contact us at [email protected] for more
information.

33 changes: 33 additions & 0 deletions src/adi/hdl/LICENSE_ADIBSD
Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@

Copyright 2011(c) Analog Devices, Inc.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
- Neither the name of Analog Devices, Inc. nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
- The use of this software may or may not infringe the patent rights
of one or more patent holders. This license does not release you
from the requirement that you obtain separate licenses from these
patent holders to use this software.
- Use of the software either in source or binary form, must be run
on or directly connected to an Analog Devices Inc. component.

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED.

IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Loading