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Updates#105

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Commits on May 19, 2019

• Don't keep generated 7020 bitstream in version control.

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• Add parallella_base intermediate files to gitignore

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Commits on May 21, 2019

• parallella/fpga: Set CFG_PLATFORM to "ZYNQ"

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• common: oh_mux: Fix Vivado issues

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• elink: Fix I/O primitives for Zynq

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• parallella/fpga: Regenerate block design scripts

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• xilibs: Upgrade IPs to Vivado 2018.2

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Commits on May 25, 2019

• parallella/fpga: Fix Makefile clean target

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• Don't keep generated 7020 bitstream in version control

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Commits on May 26, 2019

• parallella/fpga: Use offset 0 over 8 for hdmi_d pins

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• parallella/fpga: Add hdmi_e16_z7020 project

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• ip: fifo_async_104x32: Use GLOBAL synthesis flow

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• parallella/fpga: Use same net names across block designs

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• adi: Import ADI HDL IP:s needed by HDMI designs

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• adi: Add Makefile

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• parallella/fpga: Makefile: Build ADI ips

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• parallella/fpga: Use in-tree ADI IP repo

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• parallella/fpga: hdmi: Fix too long net name warnings

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• parallella/fpga: Add hdmi_e16_z7010 project

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• adi: hdl: Import axi_dmac IP

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• adi: hdl: Add dependencies needed by axi_dmac

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• adi: hdl: Add xi_dmac IP to Makefile

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• parallella/fpga: hdmi: Mimic ADI reference design

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Commits on May 27, 2019

• parallella/fpga: hdmi z7010: Try fixing clock implementation error

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• oh_memory_ram: Use LUTs over BRAM on ZYNQ

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• parallella/fgpa: HDMI: Use same SPDIF clock config for z7010 and z7020

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• parallella/fpga: HDMI: Minor visual block design improvements

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• parallella/fpga: Fix typo in Makefile clean target

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• parallella/fpga: parallella_base Add more files to clean target

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Commits on May 28, 2019

• parallella/fpga: Fix timing warning

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