[WIP] New $print cell for representing print statements #2459
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This PR introduces a new cell,
$print
, which can losslessly represent the behavior of Verilog formatting tasks like$display
inalways
blocks, both clocked and continuous. It adds support for parsing Verilog tasks$display
(as well asb
,o
,h
suffix variants) and$write
(as well asb
,o
,h
suffix variants) such that they are translated to$print
cells, and emitting$print
cells as appropriatealways
blocks containing a$write
task.As a side effect, this PR greatly improves conformance with the Verilog LRM for the
$display
and$write
family tasks used ininitial
blocks, as well as the$sformatf
function. Unfortunately, the latter improvement is likely a breaking change.Internally, this PR adds an abstract representation of format strings with substitutions that supports RTLIL and Veriog (de)serialization. It specifically does not use Verilog format strings anywhere but on the boundary. This is necessary because IEEE 1800-2017 does not precisely define the semantics of almost every aspect of its formatting facility, and real-world implementations wildly disagree with each other on even the grammar they accept.
The format string representation added by this PR is a new one I designed specifically for this task. It heavily borrows from Python f-strings (in particular, the method of escaping the substitutions is exactly identical) and is designed for simplicity of programmatic use and human readability, in that order.
Remaining work:
Fmt::render
facility used by Yosys to print messages when it encountersinitial $display
statements and for$sformatf
.$print
cell.$print
cell and its format string mini-language.$print
cell handling in CXXRTL.%m
support that existed in the old$display
implementation (as an alias of%l
) but was removed because it is unclear whether this implementation is correct.$time
and%t
support to format strings.