Feature request: $display cell

[jeanthom]

A few persons (including myself) have expressed the need for a $display cell that would allow to write things on a console from inside a module (like $display in Verilog). This would make debugging far easier.

Related issue in nMigen: amaranth-lang/amaranth#432

[mwkmwkmwk]

Could you tell us more about the cell you'd want? What would be the inputs and semantics? Which parts of yosys should support it? (I'd guess Verilog frontend, cxxrtl, Verilog backend?)

[whitequark]

@mwkmwkmwk Didn't we discuss it in a meeting a few weeks ago?

[whitequark]

I believe the semantics we worked out was along the lines of:

module $display(...);
    parameter CLK_ENABLE = 1'b0;
    parameter CLK_POLARITY = 1'b0;
    parameter FORMAT_WIDTH;
    parameter ARGS_WIDTH;
    parameter ARGS_LAYOUT;
    input CLK;
    input EN;
    input [FORMAT_WIDTH:0] FORMAT;
    input [ARGS_WIDTH:0] ARGS;
endmodule

The idea is to have a primitive that maps well to Verilog backend, CXXRTL backend, and formal verification. The function of CLK and EN is the same as elsewhere. ARGS is all of the substitutions, concatenated together. ARGS_LAYOUT is a list of argument sizes pre-concatenation (something like a space-separated list of widths as decimals), to make the argument list unambiguous without any inspection of the format strings.

Synchronous display cells trigger on the clock. Asynchronous display cells trigger on any change of inputs. (This was Claire's suggestion.)

Names subject to bikeshed, of course.

[mwkmwkmwk]

Yeah, sounds good (I just haven't seen it written down before).

[daglem]

If I understand correctly, this is handled in #2459.

[povik]

This feature has been added under the name of $print cells in #3721.