Merge pull request #3900 from YosysHQ/micko/synth_lattice

Create unified synth_lattice

passes/opt/opt_lut_ins.cc

@@ -39,7 +39,7 @@ struct OptLutInsPass : public Pass {
 		log("\n");
 		log("    -tech <technology>\n");
 		log("        Instead of generic $lut cells, operate on LUT cells specific\n");
-		log("        to the given technology.  Valid values are: xilinx, ecp5, gowin.\n");
+		log("        to the given technology.  Valid values are: xilinx, lattice, gowin.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -58,7 +58,7 @@ struct OptLutInsPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		if (techname != "" && techname != "xilinx" && techname != "ecp5" && techname != "gowin")
+		if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "ecp5" && techname != "gowin")
 			log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
 
 		for (auto module : design->selected_modules())
@@ -130,7 +130,7 @@ struct OptLutInsPass : public Pass {
 						output = cell->getPort(ID::O);
 					else
 						output = cell->getPort(ID::F);
-				} else if (techname == "ecp5") {
+				} else if (techname == "lattice" || techname == "ecp5") {
 					if (cell->type == ID(LUT4)) {
 						inputs = {
 							cell->getPort(ID::A),
@@ -181,7 +181,7 @@ struct OptLutInsPass : public Pass {
 				if (!doit)
 					continue;
 				log("  Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs));
-				if (techname == "ecp5") {
+				if (techname == "lattice" || techname == "ecp5") {
 					// Pad the LUT to 4 inputs, adding consts from the front.
 					int extra = 4 - GetSize(new_inputs);
 					log_assert(extra >= 0);
@@ -215,9 +215,9 @@ struct OptLutInsPass : public Pass {
 					}
 					new_lut[i] = lut[lidx];
 				}
-				// For ecp5, and gowin do not replace with a const driver — the nextpnr
+				// For lattice, and gowin do not replace with a const driver — the nextpnr
 				// packer requires a complete set of LUTs for wide LUT muxes.
-				if (new_inputs.empty() && techname != "ecp5" && techname != "gowin") {
+				if (new_inputs.empty() && techname != "lattice" && techname != "ecp5" && techname != "gowin") {
 					// const driver.
 					remove_cells.push_back(cell);
 					module->connect(output, new_lut[0]);
@@ -226,7 +226,7 @@ struct OptLutInsPass : public Pass {
 						cell->setParam(ID::LUT, new_lut);
 						cell->setParam(ID::WIDTH, GetSize(new_inputs));
 						cell->setPort(ID::A, new_inputs);
-					} else if (techname == "ecp5") {
+					} else if (techname == "lattice" || techname == "ecp5") {
 						log_assert(GetSize(new_inputs) == 4);
 						cell->setParam(ID::INIT, new_lut);
 						cell->setPort(ID::A, new_inputs[0]);

techlibs/ecp5/Makefile.inc

@@ -1,5 +1,5 @@
 
-OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o
+OBJS += techlibs/ecp5/synth_ecp5.o
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh))

techlibs/ecp5/synth_ecp5.cc

@@ -359,7 +359,7 @@ struct SynthEcp5Pass : public ScriptPass
 			run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
 			run("opt_expr -undriven -mux_undef");
 			run("simplemap");
-			run("ecp5_gsr");
+			run("lattice_gsr");
 			run("attrmvcp -copy -attr syn_useioff");
 			run("opt_clean");
 		}
@@ -404,7 +404,7 @@ struct SynthEcp5Pass : public ScriptPass
 				run("techmap -map +/ecp5/cells_map.v", "(skip if -vpr)");
 			else if (!vpr)
 				run("techmap -map +/ecp5/cells_map.v");
-			run("opt_lut_ins -tech ecp5");
+			run("opt_lut_ins -tech lattice");
 			run("clean");
 		}
 

techlibs/lattice/Makefile.inc

@@ -0,0 +1,27 @@
+
+OBJS += techlibs/lattice/synth_lattice.o
+OBJS += techlibs/lattice/lattice_gsr.o
+
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_ff.vh))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_io.vh))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_map.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/common_sim.vh))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2d_sim.vh))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2c_sim.vh))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_ecp5.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo2.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3d.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_ecp5.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo2.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_map.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams.txt))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_16kd.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_16kd.txt))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_8kc.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_8kc.txt))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2c.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2d.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/latches_map.v))
+$(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_18x18.v))

techlibs/lattice/arith_map_ccu2c.v

@@ -0,0 +1,90 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Claire Xenia Wolf <[email protected]>
+ *  Copyright (C) 2018  gatecat <[email protected]>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+(* techmap_celltype = "$alu" *)
+module _80_ccu2c_alu (A, B, CI, BI, X, Y, CO);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 1;
+	parameter B_WIDTH = 1;
+	parameter Y_WIDTH = 1;
+
+	(* force_downto *)
+	input [A_WIDTH-1:0] A;
+	(* force_downto *)
+	input [B_WIDTH-1:0] B;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] CO;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+	function integer round_up2;
+		input integer N;
+		begin
+			round_up2 = ((N + 1) / 2) * 2;
+		end
+	endfunction
+
+	localparam Y_WIDTH2 = round_up2(Y_WIDTH);
+
+	(* force_downto *)
+	wire [Y_WIDTH2-1:0] AA = A_buf;
+	(* force_downto *)
+	wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
+	(* force_downto *)
+	wire [Y_WIDTH2-1:0] BX = B_buf;
+	(* force_downto *)
+	wire [Y_WIDTH2-1:0] C = {CO, CI};
+	(* force_downto *)
+	wire [Y_WIDTH2-1:0] FCO, Y1;
+
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
+		CCU2C #(
+			.INIT0(16'b1001011010101010),
+			.INIT1(16'b1001011010101010),
+			.INJECT1_0("NO"),
+			.INJECT1_1("NO")
+	   ) ccu2c_i (
+			.CIN(C[i]),
+			.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),
+			.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),
+			.S0(Y[i]), .S1(Y1[i]),
+			.COUT(FCO[i])
+		);
+
+		assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
+		if (i+1 < Y_WIDTH) begin
+			assign CO[i+1] = FCO[i];
+			assign Y[i+1] = Y1[i];
+		end
+	end endgenerate
+
+	assign X = AA ^ BB;
+endmodule

techlibs/machxo2/arith_map.v → techlibs/lattice/arith_map_ccu2d.v

@@ -19,7 +19,7 @@
  */
 
 (* techmap_celltype = "$alu" *)
-module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
+module _80_ccu2d_alu (A, B, CI, BI, X, Y, CO);
 	parameter A_SIGNED = 0;
 	parameter B_SIGNED = 0;
 	parameter A_WIDTH = 1;

techlibs/lattice/brams_16kd.txt

@@ -0,0 +1,52 @@
+ram block $__DP16KD_ {
+	abits 14;
+	widths 1 2 4 9 18 per_port;
+	byte 9;
+	cost 128;
+	init no_undef;
+	port srsw "A" "B" {
+		clock anyedge;
+		clken;
+		wrbe_separate;
+		portoption "WRITEMODE" "NORMAL" {
+			rdwr no_change;
+		}
+		portoption "WRITEMODE" "WRITETHROUGH" {
+			rdwr new;
+		}
+		portoption "WRITEMODE" "READBEFOREWRITE" {
+			rdwr old;
+		}
+		option "RESETMODE" "SYNC" {
+			rdsrst zero ungated block_wr;
+		}
+		option "RESETMODE" "ASYNC" {
+			rdarst zero;
+		}
+		rdinit zero;
+	}
+}
+
+ram block $__PDPW16KD_ {
+	abits 14;
+	widths 1 2 4 9 18 36 per_port;
+	byte 9;
+	cost 128;
+	init no_undef;
+	port sr "R" {
+		clock anyedge;
+		clken;
+		option "RESETMODE" "SYNC" {
+			rdsrst zero ungated;
+		}
+		option "RESETMODE" "ASYNC" {
+			rdarst zero;
+		}
+		rdinit zero;
+	}
+	port sw "W" {
+		width 36;
+		clock anyedge;
+		clken;
+	}
+}