enable more primitives supported with nextpnr

YosysHQ · Aug 25, 2023 · 0756285 · 0756285
1 parent 3b9ebfa
commit 0756285
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Showing 5 changed files with 135 additions and 18 deletions.
diff --git a/techlibs/lattice/cells_bb_xo2.v b/techlibs/lattice/cells_bb_xo2.v
@@ -408,6 +408,17 @@ module FIFO8KB (...);
     output FF;
 endmodule
 
+(* blackbox *)
+module CLKDIVC (...);
+    parameter GSR = "DISABLED";
+    parameter DIV = "2.0";
+    input RST;
+    input CLKI;
+    input ALIGNWD;
+    output CDIV1;
+    output CDIVX;
+endmodule
+
 (* blackbox *)
 module DCMA (...);
     input CLK0;
@@ -416,13 +427,33 @@ module DCMA (...);
     output DCMOUT;
 endmodule
 
+(* blackbox *)
+module ECLKSYNCA (...);
+    input ECLKI;
+    input STOP;
+    output ECLKO;
+endmodule
+
+(* blackbox *)
+module ECLKBRIDGECS (...);
+    input CLK0;
+    input CLK1;
+    input SEL;
+    output ECSOUT;
+endmodule
+
 (* blackbox *)
 module DCCA (...);
     input CLKI;
     input CE;
     output CLKO;
 endmodule
 
+(* blackbox *) (* keep *)
+module START (...);
+    input STARTCLK;
+endmodule
+
 (* blackbox *)
 module EHXPLLJ (...);
     parameter CLKI_DIV = 1;
@@ -533,3 +564,8 @@ module OSCH (...);
     output SEDSTDBY;
 endmodule
 
+(* blackbox *) (* keep *)
+module TSALL (...);
+    input TSALL;
+endmodule
+
diff --git a/techlibs/lattice/cells_bb_xo3.v b/techlibs/lattice/cells_bb_xo3.v
@@ -408,6 +408,17 @@ module FIFO8KB (...);
     output FF;
 endmodule
 
+(* blackbox *)
+module CLKDIVC (...);
+    parameter GSR = "DISABLED";
+    parameter DIV = "2.0";
+    input RST;
+    input CLKI;
+    input ALIGNWD;
+    output CDIV1;
+    output CDIVX;
+endmodule
+
 (* blackbox *)
 module DCMA (...);
     input CLK0;
@@ -416,13 +427,33 @@ module DCMA (...);
     output DCMOUT;
 endmodule
 
+(* blackbox *)
+module ECLKSYNCA (...);
+    input ECLKI;
+    input STOP;
+    output ECLKO;
+endmodule
+
+(* blackbox *)
+module ECLKBRIDGECS (...);
+    input CLK0;
+    input CLK1;
+    input SEL;
+    output ECSOUT;
+endmodule
+
 (* blackbox *)
 module DCCA (...);
     input CLKI;
     input CE;
     output CLKO;
 endmodule
 
+(* blackbox *) (* keep *)
+module START (...);
+    input STARTCLK;
+endmodule
+
 (* blackbox *)
 module EHXPLLJ (...);
     parameter CLKI_DIV = 1;
@@ -533,3 +564,8 @@ module OSCH (...);
     output SEDSTDBY;
 endmodule
 
+(* blackbox *) (* keep *)
+module TSALL (...);
+    input TSALL;
+endmodule
+
diff --git a/techlibs/lattice/cells_bb_xo3d.v b/techlibs/lattice/cells_bb_xo3d.v
@@ -408,6 +408,17 @@ module FIFO8KB (...);
     output FF;
 endmodule
 
+(* blackbox *)
+module CLKDIVC (...);
+    parameter GSR = "DISABLED";
+    parameter DIV = "2.0";
+    input RST;
+    input CLKI;
+    input ALIGNWD;
+    output CDIV1;
+    output CDIVX;
+endmodule
+
 (* blackbox *)
 module DCMA (...);
     input CLK0;
@@ -416,13 +427,33 @@ module DCMA (...);
     output DCMOUT;
 endmodule
 
+(* blackbox *)
+module ECLKSYNCA (...);
+    input ECLKI;
+    input STOP;
+    output ECLKO;
+endmodule
+
+(* blackbox *)
+module ECLKBRIDGECS (...);
+    input CLK0;
+    input CLK1;
+    input SEL;
+    output ECSOUT;
+endmodule
+
 (* blackbox *)
 module DCCA (...);
     input CLKI;
     input CE;
     output CLKO;
 endmodule
 
+(* blackbox *) (* keep *)
+module START (...);
+    input STARTCLK;
+endmodule
+
 (* blackbox *)
 module EHXPLLJ (...);
     parameter CLKI_DIV = 1;
@@ -534,3 +565,8 @@ module OSCJ (...);
     output OSCESB;
 endmodule
 
+(* blackbox *) (* keep *)
+module TSALL (...);
+    input TSALL;
+endmodule
+
diff --git a/techlibs/lattice/cells_xtra.py b/techlibs/lattice/cells_xtra.py
@@ -315,13 +315,13 @@ class State(Enum):
         Cell("PDPW8KC"),
         Cell("SP8KC"),
         Cell("FIFO8KB"),
-        #Cell("CLKDIVC"),
+        Cell("CLKDIVC"),
         Cell("DCMA"),
-        #Cell("ECLKSYNCA"),
-        #Cell("ECLKBRIDGECS"),
+        Cell("ECLKSYNCA"),
+        Cell("ECLKBRIDGECS"),
         Cell("DCCA"),
-        #Cell("JTAGF"),
-        #Cell("START"),
+        #Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
+        Cell("START", True),
         #Cell("SEDFA"),
         #Cell("SEDFB"),
         #Cell("IDDRXE"),
@@ -351,7 +351,7 @@ class State(Enum):
         #Cell("PLLREFCS"),
         Cell("OSCH"),
         #Cell("EFB"),
-        #Cell("TSALL"),
+        Cell("TSALL", True),
     ]),
     ("cells_bb_xo3.v", "machxo3lf", [
         #Cell("AGEB2"),
@@ -495,13 +495,13 @@ class State(Enum):
         Cell("PDPW8KC"),
         Cell("SP8KC"),
         Cell("FIFO8KB"),
-        #Cell("CLKDIVC"),
+        Cell("CLKDIVC"),
         Cell("DCMA"),
-        #Cell("ECLKSYNCA"),
-        #Cell("ECLKBRIDGECS"),
+        Cell("ECLKSYNCA"),
+        Cell("ECLKBRIDGECS"),
         Cell("DCCA"),
-        #Cell("JTAGF"),
-        #Cell("START"),
+        #Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
+        Cell("START", True),
         #Cell("SEDFA"),
         #Cell("SEDFB"),
         #Cell("IDDRXE"),
@@ -527,7 +527,7 @@ class State(Enum):
         #Cell("PLLREFCS"),
         Cell("OSCH"),
         #Cell("EFB"),
-        #Cell("TSALL"),
+        Cell("TSALL", True),
     ]),
     ("cells_bb_xo3d.v", "machxo3d", [
         #Cell("AGEB2"),
@@ -672,13 +672,13 @@ class State(Enum):
         Cell("PDPW8KC"),
         Cell("SP8KC"),
         Cell("FIFO8KB"),
-        #Cell("CLKDIVC"),
+        Cell("CLKDIVC"),
         Cell("DCMA"),
-        #Cell("ECLKSYNCA"),
-        #Cell("ECLKBRIDGECS"),
+        Cell("ECLKSYNCA"),
+        Cell("ECLKBRIDGECS"),
         Cell("DCCA"),
-        #Cell("JTAGF"),
-        #Cell("START"),
+        #Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}),
+        Cell("START", True),
         #Cell("SEDFA"),
         #Cell("SEDFB"),
         #Cell("IDDRXE"),
@@ -704,7 +704,7 @@ class State(Enum):
         #Cell("PLLREFCS"),
         Cell("OSCJ"),
         #Cell("EFBB"),
-        #Cell("TSALL"),
+        Cell("TSALL", True),
         #Cell("ESBA"),
         #Cell("BCSLEWRATEA"),
     ])

diff --git a/techlibs/lattice/common_sim.vh b/techlibs/lattice/common_sim.vh
@@ -394,6 +394,15 @@ module TRELLIS_COMB(
 
 endmodule
 
+// Constants
+module VLO(output Z);
+	assign Z = 1'b0;
+endmodule
+
+module VHI(output Z);
+	assign Z = 1'b1;
+endmodule
+
 `ifndef NO_INCLUDES
 
 `include "cells_ff.vh"