Addressed code review comments

techlibs/lattice/synth_lattice.cc

@@ -41,7 +41,7 @@ struct SynthLatticePass : public ScriptPass
 		log("\n");
 		log("    synth_lattice [options]\n");
 		log("\n");
-		log("This command runs synthesis for Lattice FPGAs.\n");
+		log("This command runs synthesis for Lattice FPGAs (excluding iCE40 and Nexus).\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
@@ -66,10 +66,6 @@ struct SynthLatticePass : public ScriptPass
 		//log("        - lifmd: LIFMD (EXPERIMENTAL)\n");
 		//log("        - lifmdf: LIFMDF (EXPERIMENTAL)\n");
 		log("\n");
-		log("    -blif <file>\n");
-		log("        write the design to the specified BLIF file. writing of an output file\n");
-		log("        is omitted if this parameter is not specified.\n");
-		log("\n");
 		log("    -edif <file>\n");
 		log("        write the design to the specified EDIF file. writing of an output file\n");
 		log("        is omitted if this parameter is not specified.\n");
@@ -116,10 +112,6 @@ struct SynthLatticePass : public ScriptPass
 		log("    -abc9\n");
 		log("        use new ABC9 flow (EXPERIMENTAL)\n");
 		log("\n");
-		log("    -vpr\n");
-		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
-		log("        (this feature is experimental and incomplete)\n");
-		log("\n");
 		log("    -iopad\n");
 		log("        insert IO buffers\n");
 		log("\n");
@@ -137,14 +129,13 @@ struct SynthLatticePass : public ScriptPass
 		log("\n");
 	}
 
-	string top_opt, blif_file, edif_file, json_file, family;
-	bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, vpr, no_rw_check, have_dsp;
+	string top_opt, edif_file, json_file, family;
+	bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp;
 	string postfix, arith_map, brams_map, dsp_map;
 
 	void clear_flags() override
 	{
 		top_opt = "-auto-top";
-		blif_file = "";
 		edif_file = "";
 		json_file = "";
 		family = "";
@@ -158,7 +149,6 @@ struct SynthLatticePass : public ScriptPass
 		dff = false;
 		retime = false;
 		abc2 = false;
-		vpr = false;
 		abc9 = false;
 		iopad = false;
 		nodsp = false;
@@ -186,10 +176,6 @@ struct SynthLatticePass : public ScriptPass
 				family = args[++argidx];
 				continue;
 			}
-			if (args[argidx] == "-blif" && argidx+1 < args.size()) {
-				blif_file = args[++argidx];
-				continue;
-			}
 			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 				edif_file = args[++argidx];
 				continue;
@@ -250,10 +236,6 @@ struct SynthLatticePass : public ScriptPass
 				abc2 = true;
 				continue;
 			}
-			if (args[argidx] == "-vpr") {
-				vpr = true;
-				continue;
-			}
 			if (args[argidx] == "-abc9") {
 				abc9 = true;
 				continue;
@@ -461,10 +443,7 @@ struct SynthLatticePass : public ScriptPass
 
 		if (check_label("map_cells"))
 		{
-			if (help_mode)
-				run("techmap -map +/lattice/cells_map.v", "(skip if -vpr)");
-			else if (!vpr)
-				run("techmap -map +/lattice/cells_map.v");
+			run("techmap -map +/lattice/cells_map.v");
 			run("opt_lut_ins -tech lattice");
 			run("clean");
 		}
@@ -478,23 +457,6 @@ struct SynthLatticePass : public ScriptPass
 			run("blackbox =A:whitebox");
 		}
 
-		if (check_label("blif"))
-		{
-			if (!blif_file.empty() || help_mode) {
-				if (vpr || help_mode) {
-					run(stringf("opt_clean -purge"),
-							"                                 (vpr mode)");
-					run(stringf("write_blif -attr -cname -conn -param %s",
-							help_mode ? "<file-name>" : blif_file.c_str()),
-							" (vpr mode)");
-				}
-				if (!vpr)
-					run(stringf("write_blif -gates -attr -param %s",
-							help_mode ? "<file-name>" : blif_file.c_str()),
-							"       (non-vpr mode)");
-			}
-		}
-
 		if (check_label("edif"))
 		{
 			if (!edif_file.empty() || help_mode)
@@ -526,49 +488,4 @@ struct SynthEcp5Pass : public Pass
 } SynthEcp5Pass;
 */
 
-struct SynthMachXO2Pass : public Pass
-{
-	SynthMachXO2Pass() : Pass("synth_machxo2", "synthesis for MachXO2 FPGAs.") { }
-
-	void execute(std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		args[0] = "synth_lattice";
-		args.insert(args.begin()+1, std::string());
-		args.insert(args.begin()+1, std::string());
-		args[1] = "-family";
-		args[2] = "xo2";
-		Pass::call(design, args);
-	}
-} SynthMachXO2Pass;
-
-struct SynthMachXO3Pass : public Pass
-{
-	SynthMachXO3Pass() : Pass("synth_machxo3", "synthesis for MachXO3 FPGAs.") { }
-
-	void execute(std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		args[0] = "synth_lattice";
-		args.insert(args.begin()+1, std::string());
-		args.insert(args.begin()+1, std::string());
-		args[1] = "-family";
-		args[2] = "xo3";
-		Pass::call(design, args);
-	}
-} SynthMachXO3Pass;
-
-struct SynthMachXO3DPass : public Pass
-{
-	SynthMachXO3DPass() : Pass("synth_machxo3d", "synthesis for MachXO3D FPGAs.") { }
-
-	void execute(std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		args[0] = "synth_lattice";
-		args.insert(args.begin()+1, std::string());
-		args.insert(args.begin()+1, std::string());
-		args[1] = "-family";
-		args[2] = "xo3d";
-		Pass::call(design, args);
-	}
-} SynthMachXO3DPass;
-
 PRIVATE_NAMESPACE_END

tests/arch/machxo2/add_sub.ys

@@ -1,7 +1,7 @@
 read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 10 t:LUT4

tests/arch/machxo2/adffs.ys

@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
+equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
@@ -12,7 +12,7 @@ select -assert-none t:TRELLIS_FF %% t:* %D
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
+equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
@@ -22,7 +22,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
+equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
@@ -32,7 +32,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
+equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF

tests/arch/machxo2/counter.ys

@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -multiclock -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
+equiv_opt -assert -multiclock -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 4 t:CCU2D

tests/arch/machxo2/dffs.ys

@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top dff
 proc
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
@@ -12,7 +12,7 @@ select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF t:LUT4

tests/arch/machxo2/fsm.ys

@@ -3,7 +3,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut
+equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
 

tests/arch/machxo2/logic.ys

@@ -1,7 +1,7 @@
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 9 t:LUT4

tests/arch/machxo2/lutram.ys

@@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut
+equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut
 memory
 opt -full
 

tests/arch/machxo2/mux.ys

@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT4
@@ -12,7 +12,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 2 t:LUT4
@@ -22,7 +22,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 5 t:LUT4
@@ -32,7 +32,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-max 12 t:LUT4

tests/arch/machxo2/shifter.ys

@@ -2,7 +2,7 @@ read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 

tests/arch/machxo2/tribuf.ys

@@ -2,7 +2,7 @@ read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 flatten
-equiv_opt -assert -map +/lattice/cells_sim_xo2.v -map +/simcells.v synth_machxo2 # equivalency check
+equiv_opt -assert -map +/lattice/cells_sim_xo2.v -map +/simcells.v synth_lattice -family xo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_