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vmm: Set TCR.TxSZ to 16 as I want to use all the 48-bits in the VA ra…
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…nge. Also housekeeping. WIP.

Signed-off-by: TunaCici <[email protected]>
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@TunaCici
TunaCici committed Mar 24, 2024
1 parent c477e50 commit 780bbfd
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Showing 2 changed files with 60 additions and 51 deletions.
99 changes: 51 additions & 48 deletions Kernel/Include/Memory/Virtual.h
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Original file line number Diff line number Diff line change
Expand Up @@ -24,63 +24,66 @@
#define L3_BLOCK_SIZE (1UL << 12) // 4 KiB

/* Hardware page table definition */
#define PTE_TYPE_MASK (3 << 0)
#define PTE_TYPE_FAULT (0 << 0)
#define PTE_TYPE_TABLE (3 << 0)
#define PTE_TYPE_PAGE (3 << 0)
#define PTE_TYPE_BLOCK (1 << 0)
#define PTE_TYPE_VALID (1 << 0)
#define PTE_TYPE_MASK (3 << 0)
#define PTE_TYPE_FAULT (0 << 0)
#define PTE_TYPE_TABLE (3 << 0)
#define PTE_TYPE_PAGE (3 << 0)
#define PTE_TYPE_BLOCK (1 << 0)
#define PTE_TYPE_VALID (1 << 0)

#define PTE_TABLE_PXN (1UL << 59)
#define PTE_TABLE_XN (1UL << 60)
#define PTE_TABLE_AP (1UL << 61)
#define PTE_TABLE_NS (1UL << 63)
#define PTE_TABLE_PXN (1UL << 59)
#define PTE_TABLE_XN (1UL << 60)
#define PTE_TABLE_AP (1UL << 61)
#define PTE_TABLE_NS (1UL << 63)

/* Block */
#define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
#define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
#define PTE_BLOCK_NS (1 << 5)
#define PTE_BLOCK_NON_SHARE (0 << 8)
#define PTE_BLOCK_OUTER_SHARE (2 << 8)
#define PTE_BLOCK_INNER_SHARE (3 << 8)
#define PTE_BLOCK_AF (1 << 10)
#define PTE_BLOCK_NG (1 << 11)
#define PTE_BLOCK_PXN (UL(1) << 53)
#define PTE_BLOCK_UXN (UL(1) << 54)
#define PTE_BLOCK_NON_SHARE (0 << 8)
#define PTE_BLOCK_OUTER_SHARE (2 << 8)
#define PTE_BLOCK_INNER_SHARE (3 << 8)
#define PTE_BLOCK_AF (1 << 10)
#define PTE_BLOCK_NG (1 << 11)
#define PTE_BLOCK_PXN (UL(1) << 53)
#define PTE_BLOCK_UXN (UL(1) << 54)

/* AttrIndx[2:0] */
#define PMD_ATTRINDX(t) ((t) << 2)
#define PMD_ATTRINDX_MASK (7 << 2)
#define PMD_ATTRMASK (PTE_BLOCK_PXN | \
PTE_BLOCK_UXN | \
PMD_ATTRINDX_MASK | \
PTE_TYPE_VALID)
#define PMD_ATTRINDX(t) ((t) << 2)
#define PMD_ATTRINDX_MASK (7 << 2)
#define PMD_ATTRMASK (PTE_BLOCK_PXN | \
PTE_BLOCK_UXN | \
PMD_ATTRINDX_MASK | \
PTE_TYPE_VALID)

/* TCR flags */
#define TCR_T0SZ(x) ((64 - (x)) << 0)
#define TCR_IRGN_NC (0 << 8)
#define TCR_IRGN_WBWA (1 << 8)
#define TCR_IRGN_WT (2 << 8)
#define TCR_IRGN_WBNWA (3 << 8)
#define TCR_IRGN_MASK (3 << 8)
#define TCR_ORGN_NC (0 << 10)
#define TCR_ORGN_WBWA (1 << 10)
#define TCR_ORGN_WT (2 << 10)
#define TCR_ORGN_WBNWA (3 << 10)
#define TCR_ORGN_MASK (3 << 10)
#define TCR_SHARED_NON (0 << 12)
#define TCR_SHARED_OUTER (2 << 12)
#define TCR_SHARED_INNER (3 << 12)
#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG0_16K (2 << 14)
#define TCR_EPD1_DISABLE (1 << 23)
#define TCR_DS_48BITS ~(1UL << 59)
#define TCR_DS_52BITS (1UL << 59)
#define TCR_IPS_SHIFT (32)
#define TCR_T1SZ (16) // 2^(64 - T1SZ) bits for TTBR1
#define TCR_T0SZ (16) // 2^(64 - T0SZ) bits for TTBR0
#define TCR_IRGN_NC (0 << 8)
#define TCR_IRGN_WBWA (1 << 8)
#define TCR_IRGN_WT (2 << 8)
#define TCR_IRGN_WBNWA (3 << 8)
#define TCR_IRGN_MASK (3 << 8)
#define TCR_ORGN_NC (0 << 10)
#define TCR_ORGN_WBWA (1 << 10)
#define TCR_ORGN_WT (2 << 10)
#define TCR_ORGN_WBNWA (3 << 10)
#define TCR_ORGN_MASK (3 << 10)
#define TCR_SHARED_NON (0 << 12)
#define TCR_SHARED_OUTER (2 << 12)
#define TCR_SHARED_INNER (3 << 12)
#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG0_16K (2 << 14)
#define TCR_EPD1_DISABLE (1 << 23)
#define TCR_DS_48BITS ~(1UL << 59)
#define TCR_DS_52BITS (1UL << 59)
#define TCR_T1SZ_SHIFT (0)
#define TCR_T0SZ_SHIFT (16)
#define TCR_IPS_SHIFT (32)

#define TCR_EL1_RSVD (1 << 31)
#define TCR_EL2_RSVD (1 << 31 | 1 << 23)
#define TCR_EL3_RSVD (1 << 31 | 1 << 23)
#define TCR_EL1_RSVD (1 << 31)
#define TCR_EL2_RSVD (1 << 31 | 1 << 23)
#define TCR_EL3_RSVD (1 << 31 | 1 << 23)

void init_kernel_pgtbl(void);
void init_tcr(void);
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12 changes: 9 additions & 3 deletions Kernel/Memory/Virtual.c
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Original file line number Diff line number Diff line change
Expand Up @@ -60,21 +60,27 @@ void init_tcr(void)
MRS("TCR_EL1", tcr_el1);
isb();

/* DS: output addr (OA) and virtual addr (VA) size set to 48-bit */
/* DS: max. output addr (OA) and virtual addr (VA) size set to 48-bit */
tcr_el1 &= TCR_DS_48BITS;

/* IPS: intrmdt. output addr (OA) set to ID_AA64MMFR0_EL1.PARange */
/* IPS: effective output addr (OA) set to ID_AA64MMFR0_EL1.PARange */
MRS("ID_AA64MMFR0_EL1", reg);
tcr_el1 |= (GET_PARange(reg) << TCR_IPS_SHIFT);

/* T1SZ: input address (IA) size offset of memory region for TTBR1_EL1 */
tcr_el1 |= TCR_T1SZ << TCR_T1SZ_SHIFT;

/* T0SZ: input address (IA) size offset of memory region for TTBR0_EL1 */
tcr_el1 |= TCR_T0SZ << TCR_T0SZ_SHIFT;

/* Save TCR_EL1 */
MSR("TCR_EL1", tcr_el1);
isb();

/* DEBUG TCR_EL1 */
MRS("TCR_EL1", tcr_el1);
isb();
klog("[vmm] Intermediate Physical Address Size: 0x%lx\n", (tcr_el1 >> 32) & 0b111);
klog("[vmm] TCR_EL1: 0x%lx\n", tcr_el1);

}

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