vmm: Setting up TCR_EL1's DS and IPS values. WIP.

Signed-off-by: TunaCici <[email protected]>
TunaCici · Mar 24, 2024 · c477e50 · c477e50
1 parent a5d5fef
commit c477e50
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Showing 3 changed files with 29 additions and 1 deletion.
diff --git a/Kernel/Include/Memory/Virtual.h b/Kernel/Include/Memory/Virtual.h
@@ -74,6 +74,9 @@
 #define TCR_TG0_64K		(1 << 14)
 #define TCR_TG0_16K		(2 << 14)
 #define TCR_EPD1_DISABLE	(1 << 23)
+#define TCR_DS_48BITS		~(1UL << 59)
+#define TCR_DS_52BITS		(1UL << 59)
+#define TCR_IPS_SHIFT		(32)
 
 #define TCR_EL1_RSVD		(1 << 31)
 #define TCR_EL2_RSVD		(1 << 31 | 1 << 23)

diff --git a/Kernel/Main.c b/Kernel/Main.c
@@ -76,6 +76,7 @@ void kmain(void)
 
         /* 3. Init Kernel Page Tables & Enable MMU */
         init_kernel_pgtbl();
+        init_tcr();
 
         /* X. Do something weird */
         klog("[kmain] imma just sleep\n");

diff --git a/Kernel/Memory/Virtual.c b/Kernel/Memory/Virtual.c
@@ -2,9 +2,14 @@
  * Virtual memory manager for the ARMv8-A architecture
  *
  * References:
+ * https://developer.arm.com/documentation/ddi0487/ka 
  * https://developer.arm.com/documentation/den0024/a/The-Memory-Management-Unit
  * https://github.com/ARM-software/u-boot/blob/master/arch/arm/include/asm/armv8/mmu.h
  * https://lowenware.com/blog/aarch64-mmu-programming/
+ * https://armv8-ref.codingbelief.com/en/
+ *
+ * See below on how overcome ASID's limit of 256 diff tasks in TLB
+ * https://stackoverflow.com/questions/17590146
  *
  * Author: Tuna CICI
  */
@@ -26,6 +31,7 @@ void init_kernel_pgtbl(void)
 {
         uint64_t ttbr1 = 0;
 
+        /* TODO: THIS IS WRONG. FIX COMING */
         /* Identity mapping for the kernel */
         for (uint32_t i = 0; i < ENTRY_SIZE; i++) {
                 l0_kernel_pgtbl[i] = (void *) (i * L0_BLOCK_SIZE);
@@ -47,11 +53,29 @@ void init_kernel_pgtbl(void)
 
 void init_tcr(void)
 {
-        /* TODO */
         uint64_t tcr_el1 = 0;
+        uint64_t reg = 0;
+
+        /* Read TCR_EL1 */
+        MRS("TCR_EL1", tcr_el1);
+        isb();
+
+        /* DS: output addr (OA) and virtual addr (VA) size set to 48-bit */
+        tcr_el1 &= TCR_DS_48BITS;
 
+        /* IPS: intrmdt. output addr (OA) set to ID_AA64MMFR0_EL1.PARange */
+        MRS("ID_AA64MMFR0_EL1", reg);
+        tcr_el1 |= (GET_PARange(reg) << TCR_IPS_SHIFT);
+
+        /* Save TCR_EL1 */
         MSR("TCR_EL1", tcr_el1);
         isb();
+
+        /* DEBUG TCR_EL1 */
+        MRS("TCR_EL1", tcr_el1);
+        isb();
+        klog("[vmm] Intermediate Physical Address Size: 0x%lx\n", (tcr_el1 >> 32) & 0b111);
+
 }
 
 void init_mair(void)