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feat: update project tt_um_MNSLab_BLDC from BatuCem/tt06-mnslab-bldc-0
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Commit: 5a10ee17659392b25ff2b849a595f0d450e4678a
Workflow: https://github.com/BatuCem/tt06-mnslab-bldc-0/actions/runs/8725171340
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TinyTapeoutBot authored and urish committed Apr 17, 2024
1 parent bc56cc6 commit 92a104c
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6 changes: 3 additions & 3 deletions projects/tt_um_MNSLab_BLDC/commit_id.json
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt06 d5153c3f",
"app": "Tiny Tapeout tt06 bc500a3a",
"repo": "https://github.com/BatuCem/tt06-mnslab-bldc-0",
"commit": "0e6f66b0837e288482339b3ec3c79b4fb601f96a",
"workflow_url": "https://github.com/BatuCem/tt06-mnslab-bldc-0/actions/runs/8693585600",
"commit": "5a10ee17659392b25ff2b849a595f0d450e4678a",
"workflow_url": "https://github.com/BatuCem/tt06-mnslab-bldc-0/actions/runs/8725171340",
"sort_id": 1713204750795,
"openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
"pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
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5 changes: 2 additions & 3 deletions projects/tt_um_MNSLab_BLDC/info.yaml
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
# Tiny Tapeout project information
project:
title: "Universal Motor and Actuator Controller" # Project title
author: "Dinçer Gökcen, Ethem Buğra Arslan, Batu Cem Özyurt" # Your name
author: "Assoc. Prof. Dinçer Gökcen, Ethem Buğra Arslan, Batu Cem Özyurt" # Your name
discord: "batucem" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "bldc motor controller and autotuner for controller by MNS lab" # One line description of what your project does
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 25000000 # Clock frequency in Hz (or 0 if not applicable)
clock_hz: 50000000 # Clock frequency in Hz (or 0 if not applicable)

# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "4x2" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
Expand All @@ -17,7 +17,6 @@ project:
source_files:
- "project.v"
- "bldc_esc.v"
- "Divided_Clock.v"
- "Divider32bit.v"
- "I2C_SLAVE_4.v"
- "pid_tuner.v"
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2 changes: 1 addition & 1 deletion projects/tt_um_MNSLab_BLDC/stats/metrics.csv
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/work/src,tt_um_MNSLab_BLDC,wokwi,flow completed,0h11m48s0ms,0h9m18s0ms,108504.93473331493,0.1541128064,54252.46736665747,54.26,52.544599999999996,858.12,7780,0,0,0,0,0,0,0,1,1,0,-1,-1,225203,58362,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,171411007.0,0.0,56.39,35.24,12.35,1.76,-1,7539,9139,203,1559,0,0,0,8403,549,21,262,504,1048,1274,434,554,953,949,28,6860,2158,13,3513,8361,20905,149183.0784,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,153.18,153.6,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
/work/src,tt_um_MNSLab_BLDC,wokwi,flow completed,0h11m54s0ms,0h9m23s0ms,109659.9328425441,0.1541128064,54829.96642127205,54.75,54.39810000000001,816.9,7738,0,0,0,0,0,0,0,2,2,0,-1,-1,237523,60118,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,180800045.0,0.0,58.92,37.23,14.28,1.37,-1,7673,9220,198,1559,0,0,0,8521,535,19,272,508,1093,1264,445,551,959,954,29,6712,2158,14,3543,8450,20877,149183.0784,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,153.18,153.6,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
151 changes: 75 additions & 76 deletions projects/tt_um_MNSLab_BLDC/stats/synthesis-stats.txt
Original file line number Diff line number Diff line change
@@ -1,91 +1,90 @@

70. Printing statistics.
69. Printing statistics.

=== tt_um_MNSLab_BLDC ===

Number of wires: 7764
Number of wire bits: 7799
Number of public wires: 937
Number of public wire bits: 972
Number of wires: 7722
Number of wire bits: 7757
Number of public wires: 942
Number of public wire bits: 977
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 7780
sky130_fd_sc_hd__a2111o_2 5
sky130_fd_sc_hd__a2111oi_2 2
sky130_fd_sc_hd__a211o_2 74
sky130_fd_sc_hd__a211oi_2 26
sky130_fd_sc_hd__a21bo_2 44
Number of cells: 7738
sky130_fd_sc_hd__a2111o_2 11
sky130_fd_sc_hd__a2111oi_2 1
sky130_fd_sc_hd__a211o_2 68
sky130_fd_sc_hd__a211oi_2 21
sky130_fd_sc_hd__a21bo_2 33
sky130_fd_sc_hd__a21boi_2 17
sky130_fd_sc_hd__a21o_2 224
sky130_fd_sc_hd__a21oi_2 198
sky130_fd_sc_hd__a221o_2 73
sky130_fd_sc_hd__a22o_2 335
sky130_fd_sc_hd__a22oi_2 62
sky130_fd_sc_hd__a21o_2 278
sky130_fd_sc_hd__a21oi_2 162
sky130_fd_sc_hd__a221o_2 84
sky130_fd_sc_hd__a221oi_2 3
sky130_fd_sc_hd__a22o_2 425
sky130_fd_sc_hd__a22oi_2 79
sky130_fd_sc_hd__a2bb2o_2 32
sky130_fd_sc_hd__a2bb2oi_2 2
sky130_fd_sc_hd__a311o_2 15
sky130_fd_sc_hd__a311oi_2 1
sky130_fd_sc_hd__a31o_2 109
sky130_fd_sc_hd__a31oi_2 8
sky130_fd_sc_hd__a32o_2 22
sky130_fd_sc_hd__a32oi_2 1
sky130_fd_sc_hd__a311o_2 8
sky130_fd_sc_hd__a311oi_2 3
sky130_fd_sc_hd__a31o_2 106
sky130_fd_sc_hd__a31oi_2 12
sky130_fd_sc_hd__a32o_2 71
sky130_fd_sc_hd__a32oi_2 3
sky130_fd_sc_hd__a41o_2 6
sky130_fd_sc_hd__a41oi_2 1
sky130_fd_sc_hd__and2_2 287
sky130_fd_sc_hd__and2b_2 147
sky130_fd_sc_hd__and3_2 197
sky130_fd_sc_hd__and3b_2 58
sky130_fd_sc_hd__and4_2 111
sky130_fd_sc_hd__and4b_2 29
sky130_fd_sc_hd__and4bb_2 15
sky130_fd_sc_hd__buf_1 750
sky130_fd_sc_hd__and2_2 240
sky130_fd_sc_hd__and2b_2 144
sky130_fd_sc_hd__and3_2 171
sky130_fd_sc_hd__and3b_2 43
sky130_fd_sc_hd__and4_2 114
sky130_fd_sc_hd__and4b_2 28
sky130_fd_sc_hd__and4bb_2 6
sky130_fd_sc_hd__buf_1 661
sky130_fd_sc_hd__buf_2 4
sky130_fd_sc_hd__conb_1 21
sky130_fd_sc_hd__dfxtp_2 932
sky130_fd_sc_hd__ebufn_2 1
sky130_fd_sc_hd__inv_2 259
sky130_fd_sc_hd__mux2_2 268
sky130_fd_sc_hd__mux4_2 65
sky130_fd_sc_hd__nand2_2 588
sky130_fd_sc_hd__nand2b_2 2
sky130_fd_sc_hd__nand3_2 72
sky130_fd_sc_hd__nand3b_2 11
sky130_fd_sc_hd__nand4_2 20
sky130_fd_sc_hd__nand4b_2 1
sky130_fd_sc_hd__nor2_2 475
sky130_fd_sc_hd__conb_1 20
sky130_fd_sc_hd__dfxtp_2 938
sky130_fd_sc_hd__inv_2 270
sky130_fd_sc_hd__mux2_2 260
sky130_fd_sc_hd__mux4_2 64
sky130_fd_sc_hd__nand2_2 654
sky130_fd_sc_hd__nand3_2 62
sky130_fd_sc_hd__nand3b_2 1
sky130_fd_sc_hd__nand4_2 19
sky130_fd_sc_hd__nor2_2 476
sky130_fd_sc_hd__nor2b_2 3
sky130_fd_sc_hd__nor3_2 28
sky130_fd_sc_hd__nor3b_2 4
sky130_fd_sc_hd__nor4_2 3
sky130_fd_sc_hd__o2111a_2 6
sky130_fd_sc_hd__o211a_2 239
sky130_fd_sc_hd__o211ai_2 26
sky130_fd_sc_hd__o21a_2 144
sky130_fd_sc_hd__o21ai_2 168
sky130_fd_sc_hd__o21ba_2 74
sky130_fd_sc_hd__o21bai_2 20
sky130_fd_sc_hd__o221a_2 76
sky130_fd_sc_hd__o221ai_2 4
sky130_fd_sc_hd__o22a_2 43
sky130_fd_sc_hd__o22ai_2 4
sky130_fd_sc_hd__o2bb2a_2 32
sky130_fd_sc_hd__o311a_2 10
sky130_fd_sc_hd__o311ai_2 1
sky130_fd_sc_hd__o31a_2 21
sky130_fd_sc_hd__o31ai_2 5
sky130_fd_sc_hd__o32a_2 8
sky130_fd_sc_hd__nor3_2 23
sky130_fd_sc_hd__nor3b_2 1
sky130_fd_sc_hd__nor4_2 5
sky130_fd_sc_hd__nor4b_2 1
sky130_fd_sc_hd__o2111a_2 3
sky130_fd_sc_hd__o2111ai_2 1
sky130_fd_sc_hd__o211a_2 184
sky130_fd_sc_hd__o211ai_2 32
sky130_fd_sc_hd__o21a_2 135
sky130_fd_sc_hd__o21ai_2 154
sky130_fd_sc_hd__o21ba_2 80
sky130_fd_sc_hd__o21bai_2 24
sky130_fd_sc_hd__o221a_2 83
sky130_fd_sc_hd__o221ai_2 3
sky130_fd_sc_hd__o22a_2 41
sky130_fd_sc_hd__o22ai_2 3
sky130_fd_sc_hd__o2bb2a_2 22
sky130_fd_sc_hd__o311a_2 17
sky130_fd_sc_hd__o311ai_2 2
sky130_fd_sc_hd__o31a_2 26
sky130_fd_sc_hd__o31ai_2 8
sky130_fd_sc_hd__o32a_2 9
sky130_fd_sc_hd__o32ai_2 1
sky130_fd_sc_hd__o41a_2 2
sky130_fd_sc_hd__or2_2 380
sky130_fd_sc_hd__or2b_2 143
sky130_fd_sc_hd__or3_2 103
sky130_fd_sc_hd__or3b_2 36
sky130_fd_sc_hd__or4_2 43
sky130_fd_sc_hd__or4b_2 18
sky130_fd_sc_hd__or4bb_2 1
sky130_fd_sc_hd__xnor2_2 405
sky130_fd_sc_hd__xor2_2 159
sky130_fd_sc_hd__o41a_2 3
sky130_fd_sc_hd__o41ai_2 1
sky130_fd_sc_hd__or2_2 323
sky130_fd_sc_hd__or2b_2 154
sky130_fd_sc_hd__or3_2 92
sky130_fd_sc_hd__or3b_2 27
sky130_fd_sc_hd__or4_2 52
sky130_fd_sc_hd__or4b_2 16
sky130_fd_sc_hd__or4bb_2 3
sky130_fd_sc_hd__xnor2_2 437
sky130_fd_sc_hd__xor2_2 171

Chip area for module '\tt_um_MNSLab_BLDC': 79158.419200
Chip area for module '\tt_um_MNSLab_BLDC': 79866.598400

Binary file modified projects/tt_um_MNSLab_BLDC/tt_um_MNSLab_BLDC.gds
Binary file not shown.
114 changes: 56 additions & 58 deletions projects/tt_um_MNSLab_BLDC/tt_um_MNSLab_BLDC.lef
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@ MACRO tt_um_MNSLab_BLDC
PIN rst_n
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
ANTENNAGATEAREA 0.247500 ;
PORT
LAYER met4 ;
RECT 151.190 224.760 151.490 225.760 ;
Expand Down Expand Up @@ -452,65 +452,63 @@ MACRO tt_um_MNSLab_BLDC
LAYER li1 ;
RECT 2.760 2.635 679.880 223.125 ;
LAYER met1 ;
RECT 2.760 1.740 679.880 223.680 ;
RECT 2.760 1.740 680.180 223.280 ;
LAYER met2 ;
RECT 4.230 1.710 677.480 224.245 ;
RECT 4.230 1.710 678.400 224.925 ;
LAYER met3 ;
RECT 3.950 2.555 670.615 224.225 ;
LAYER met4 ;
RECT 4.690 224.360 7.270 224.760 ;
RECT 8.370 224.360 10.950 224.760 ;
RECT 12.050 224.360 14.630 224.760 ;
RECT 15.730 224.360 18.310 224.760 ;
RECT 19.410 224.360 21.990 224.760 ;
RECT 23.090 224.360 25.670 224.760 ;
RECT 26.770 224.360 29.350 224.760 ;
RECT 30.450 224.360 33.030 224.760 ;
RECT 34.130 224.360 36.710 224.760 ;
RECT 37.810 224.360 40.390 224.760 ;
RECT 41.490 224.360 44.070 224.760 ;
RECT 45.170 224.360 47.750 224.760 ;
RECT 48.850 224.360 51.430 224.760 ;
RECT 52.530 224.360 55.110 224.760 ;
RECT 56.210 224.360 58.790 224.760 ;
RECT 59.890 224.360 62.470 224.760 ;
RECT 63.570 224.360 66.150 224.760 ;
RECT 67.250 224.360 69.830 224.760 ;
RECT 70.930 224.360 73.510 224.760 ;
RECT 74.610 224.360 77.190 224.760 ;
RECT 78.290 224.360 80.870 224.760 ;
RECT 81.970 224.360 84.550 224.760 ;
RECT 85.650 224.360 88.230 224.760 ;
RECT 89.330 224.360 91.910 224.760 ;
RECT 93.010 224.360 95.590 224.760 ;
RECT 96.690 224.360 99.270 224.760 ;
RECT 100.370 224.360 102.950 224.760 ;
RECT 104.050 224.360 106.630 224.760 ;
RECT 107.730 224.360 110.310 224.760 ;
RECT 111.410 224.360 113.990 224.760 ;
RECT 115.090 224.360 117.670 224.760 ;
RECT 118.770 224.360 121.350 224.760 ;
RECT 122.450 224.360 125.030 224.760 ;
RECT 126.130 224.360 128.710 224.760 ;
RECT 129.810 224.360 132.390 224.760 ;
RECT 133.490 224.360 136.070 224.760 ;
RECT 137.170 224.360 139.750 224.760 ;
RECT 140.850 224.360 143.430 224.760 ;
RECT 144.530 224.360 147.110 224.760 ;
RECT 148.210 224.360 150.790 224.760 ;
RECT 151.890 224.360 154.470 224.760 ;
RECT 155.570 224.360 158.150 224.760 ;
RECT 159.250 224.360 610.585 224.760 ;
RECT 3.975 223.680 610.585 224.360 ;
RECT 3.975 12.415 17.880 223.680 ;
RECT 20.280 12.415 94.680 223.680 ;
RECT 97.080 12.415 171.480 223.680 ;
RECT 173.880 12.415 248.280 223.680 ;
RECT 250.680 12.415 325.080 223.680 ;
RECT 327.480 12.415 401.880 223.680 ;
RECT 404.280 12.415 478.680 223.680 ;
RECT 481.080 12.415 555.480 223.680 ;
RECT 557.880 12.415 610.585 223.680 ;
RECT 3.950 2.555 666.015 224.905 ;
LAYER met4 ;
RECT 4.690 224.360 7.270 224.905 ;
RECT 8.370 224.360 10.950 224.905 ;
RECT 12.050 224.360 14.630 224.905 ;
RECT 15.730 224.360 18.310 224.905 ;
RECT 19.410 224.360 21.990 224.905 ;
RECT 23.090 224.360 25.670 224.905 ;
RECT 26.770 224.360 29.350 224.905 ;
RECT 30.450 224.360 33.030 224.905 ;
RECT 34.130 224.360 36.710 224.905 ;
RECT 37.810 224.360 40.390 224.905 ;
RECT 41.490 224.360 44.070 224.905 ;
RECT 45.170 224.360 47.750 224.905 ;
RECT 48.850 224.360 51.430 224.905 ;
RECT 52.530 224.360 55.110 224.905 ;
RECT 56.210 224.360 58.790 224.905 ;
RECT 59.890 224.360 62.470 224.905 ;
RECT 63.570 224.360 66.150 224.905 ;
RECT 67.250 224.360 69.830 224.905 ;
RECT 70.930 224.360 73.510 224.905 ;
RECT 74.610 224.360 77.190 224.905 ;
RECT 78.290 224.360 80.870 224.905 ;
RECT 81.970 224.360 84.550 224.905 ;
RECT 85.650 224.360 88.230 224.905 ;
RECT 89.330 224.360 91.910 224.905 ;
RECT 93.010 224.360 95.590 224.905 ;
RECT 96.690 224.360 99.270 224.905 ;
RECT 100.370 224.360 102.950 224.905 ;
RECT 104.050 224.360 106.630 224.905 ;
RECT 107.730 224.360 110.310 224.905 ;
RECT 111.410 224.360 113.990 224.905 ;
RECT 115.090 224.360 117.670 224.905 ;
RECT 118.770 224.360 121.350 224.905 ;
RECT 122.450 224.360 125.030 224.905 ;
RECT 126.130 224.360 128.710 224.905 ;
RECT 129.810 224.360 132.390 224.905 ;
RECT 133.490 224.360 136.070 224.905 ;
RECT 137.170 224.360 139.750 224.905 ;
RECT 140.850 224.360 143.430 224.905 ;
RECT 144.530 224.360 147.110 224.905 ;
RECT 148.210 224.360 150.790 224.905 ;
RECT 151.890 224.360 154.470 224.905 ;
RECT 155.570 224.360 158.150 224.905 ;
RECT 159.250 224.360 421.065 224.905 ;
RECT 3.975 223.680 421.065 224.360 ;
RECT 3.975 13.095 17.880 223.680 ;
RECT 20.280 13.095 94.680 223.680 ;
RECT 97.080 13.095 171.480 223.680 ;
RECT 173.880 13.095 248.280 223.680 ;
RECT 250.680 13.095 325.080 223.680 ;
RECT 327.480 13.095 401.880 223.680 ;
RECT 404.280 13.095 421.065 223.680 ;
END
END tt_um_MNSLab_BLDC
END LIBRARY
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