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feat: update project tt_um_lisa from kdp1965/tt06-um-lisa
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Commit: 9e550c8518db3e682025030e81f49287af2eae65
Workflow: https://github.com/kdp1965/tt06-um-lisa/actions/runs/8722716987
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TinyTapeoutBot authored and urish committed Apr 17, 2024
1 parent 71a8e05 commit bc56cc6
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6 changes: 3 additions & 3 deletions projects/tt_um_lisa/commit_id.json
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
{
"app": "Tiny Tapeout tt06 eed83093",
"app": "Tiny Tapeout tt06 bc500a3a",
"repo": "https://github.com/kdp1965/tt06-um-lisa",
"commit": "842f5e695aed5924e93306a5f5adb14c5178add1",
"workflow_url": "https://github.com/kdp1965/tt06-um-lisa/actions/runs/8716376723",
"commit": "9e550c8518db3e682025030e81f49287af2eae65",
"workflow_url": "https://github.com/kdp1965/tt06-um-lisa/actions/runs/8722716987",
"sort_id": 1713187061806
}
9 changes: 5 additions & 4 deletions projects/tt_um_lisa/docs/info.md
Original file line number Diff line number Diff line change
Expand Up @@ -44,15 +44,16 @@ The following is a block diagram of the project:
* SPI/QSPI programmability (single/quad, port location, CE selects)
- (Q)SPI interface for instruction fetch
- Onboard 128 Byte RAM for DATA / DATA CACHE
- Data bus CACHE controller with 4 32-byte CACHE lines
- Data bus CACHE controller with 8 16-byte CACHE lines
- Instruction CACHE with a single 4-instruction CACHE line
- 16-bit programmable timer (with pre-divide)
- Debug UART available to LISA core also
- 8-bit Input and Output port (PORTA)
- 4-bit BIDIR port (PORTB)
- 8-bit Input port (PORTA)
- 8-bit Output port (PORTB)
- 4-bit BIDIR port (PORTC)
- I2C Master controller
- Hardware 8x8 integer multiplier
- Hardware 16/8 divider
- Hardware 16/8 or 16/16 integer divider
- Programmable I/O mux for maximum flexibility of I/O usage.

It uses a 32x32 1RW [DFFRAM](https://github.com/AUCOHL/DFFRAM) macro to implement a 128 bytes (1 kilobit) RAM module.
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24 changes: 12 additions & 12 deletions projects/tt_um_lisa/info.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -49,24 +49,24 @@ pinout:
ui[7]: "pa_in[7]/baud_set"

# Outputs
uo[0]: "pa_out[0]"
uo[1]: "pa_out[1]"
uo[2]: "pa_out[2]"
uo[3]: "pa_out[3]"
uo[4]: "pa_out[4]/tx"
uo[5]: "pa_out[5]"
uo[6]: "pa_out[6]"
uo[7]: "pa_out[7]/baud_clk"
uo[0]: "pb_out[0]"
uo[1]: "pb_out[1]"
uo[2]: "pb_out[2]"
uo[3]: "pb_out[3]"
uo[4]: "pb_out[4]/tx"
uo[5]: "pb_out[5]"
uo[6]: "pb_out[6]"
uo[7]: "pb_out[7]/baud_clk"

# Bidirectional pins
uio[0]: "ce0/ce_latch"
uio[1]: "mosi/dq1/ce0"
uio[2]: "miso/dq2/ce1"
uio[3]: "sclk"
uio[4]: "rx /pb_io[0]/scl/sda"
uio[5]: "tx /pb_io[1]/sda/scl"
uio[6]: "scl /pb_io[2]/dq2/rx"
uio[7]: "sda/pb_io[3]/dq3"
uio[4]: "rx /pc_io[0]/scl/sda"
uio[5]: "tx /pc_io[1]/sda/scl"
uio[6]: "scl /pc_io[2]/dq2/rx"
uio[7]: "sda/pc_io[3]/dq3"

# Do not change!
yaml_version: 6
304 changes: 168 additions & 136 deletions projects/tt_um_lisa/stats/metrics.json

Large diffs are not rendered by default.

276 changes: 137 additions & 139 deletions projects/tt_um_lisa/stats/synthesis-stats.json
Original file line number Diff line number Diff line change
@@ -1,180 +1,178 @@
{
"creator": "Yosys 0.38 (git sha1 543faed9c8c, clang++ 16.0.6 -fPIC -Os)",
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"invocation": "stat -json -liberty /home/runner/work/tt06-um-lisa/tt06-um-lisa/runs/wokwi/tmp/b89095d14c4d4e40bf4e4a8d289b50dc.lib ",
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}
}
},
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}
}
}
Expand Down
Binary file modified projects/tt_um_lisa/tt_um_lisa.gds
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