feat: update project tt_um_SteffenReith_PiMACTop from SteffenReith/TT…

…06_PiMac

Commit: e63a5e0f3b42d21b8bef56ef695a7ba07ca16095
Workflow: https://github.com/SteffenReith/TT06_PiMac/actions/runs/8745370239

projects/tt_um_SteffenReith_PiMACTop/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt06 c74b14ac",
   "repo": "https://github.com/SteffenReith/TT06_PiMac",
-  "commit": "89715c551892052feb8136c76f39e28d540c8fcb",
-  "workflow_url": "https://github.com/SteffenReith/TT06_PiMac/actions/runs/8733537394",
+  "commit": "e63a5e0f3b42d21b8bef56ef695a7ba07ca16095",
+  "workflow_url": "https://github.com/SteffenReith/TT06_PiMac/actions/runs/8745370239",
   "sort_id": 1710793624286,
   "openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
   "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"

projects/tt_um_SteffenReith_PiMACTop/info.yaml

@@ -1,11 +1,11 @@
 # Tiny Tapeout project information
 project:
-  title:        "PiMAC"                                                                 # Project title
-  author:       "Steffen Reith"                                                         # Your name
-  discord:      "steffenreith"                                                          # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "A simple pipelined multiply and accumulate unit to compute a*b+c"      # One line description of what your project does
-  language:     "Verilog"                                                               # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     0                                                                       # Clock frequency in Hz (or 0 if not applicable)
+  title:        "PiMAC"                                                               # Project title
+  author:       "Steffen Reith"                                                       # Your name
+  discord:      "steffenreith"                                                        # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "A simple pipelined multiply and accumulate unit to compute a*b+c"    # One line description of what your project does
+  language:     "Verilog"                                                             # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     0                                                                     # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

projects/tt_um_SteffenReith_PiMACTop/stats/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_SteffenReith_PiMACTop,wokwi,flow completed,0h0m57s0ms,0h0m41s0ms,18379.56815812221,0.01795472,9189.784079061104,9.65,12.001199999999999,503.46,131,0,0,0,0,0,0,0,0,0,0,-1,-1,2739,988,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,1917673.0,0.0,6.27,3.21,0.61,1.42,-1,112,242,32,162,0,0,0,136,4,36,16,4,16,12,16,0,36,20,4,1139,225,0,259,165,1788,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_SteffenReith_PiMACTop,wokwi,flow completed,0h0m57s0ms,0h0m41s0ms,18379.56815812221,0.01795472,9189.784079061104,9.65,12.001199999999999,503.32,131,0,0,0,0,0,0,0,0,0,0,-1,-1,2739,988,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,1917673.0,0.0,6.27,3.21,0.61,1.42,-1,112,242,32,162,0,0,0,136,4,36,16,4,16,12,16,0,36,20,4,1139,225,0,259,165,1788,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_SteffenReith_PiMACTop/tt_um_SteffenReith_PiMACTop.spef

@@ -1,6 +1,6 @@
 *SPEF "ieee 1481-1999"
 *DESIGN "tt_um_SteffenReith_PiMACTop"
-*DATE "06:43:15 Thursday April 18, 2024"
+*DATE "22:16:30 Thursday April 18, 2024"
 *VENDOR "The OpenROAD Project"
 *PROGRAM "OpenROAD"
 *VERSION "0889970d1790a2617e69f253221b8bd7626e51dc"