feat: update project tt_um_SteffenReith_ASGTop from SteffenReith/TT06…

…_ASG

Commit: d46a7949e5a7f5f3904d84a53e0f7cb90023fd2f
Workflow: https://github.com/SteffenReith/TT06_ASG/actions/runs/8745363637

projects/tt_um_SteffenReith_ASGTop/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt06 b544d27d",
+  "app": "Tiny Tapeout tt06 c74b14ac",
   "repo": "https://github.com/SteffenReith/TT06_ASG",
-  "commit": "51ce65983035eb3bece9d411746342235ec59480",
-  "workflow_url": "https://github.com/SteffenReith/TT06_ASG/actions/runs/8543613851",
+  "commit": "d46a7949e5a7f5f3904d84a53e0f7cb90023fd2f",
+  "workflow_url": "https://github.com/SteffenReith/TT06_ASG/actions/runs/8745363637",
   "sort_id": 1712170693987,
   "openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
   "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"

projects/tt_um_SteffenReith_ASGTop/docs/info.md

@@ -13,10 +13,16 @@ This is a naive implementation of an "Alternating Step Generator" (ASG) to produ
 
 An ASG consists of three different "Linear Shift Feedback Registers" (LSFR), which must be coupled appropriately. The provided configuration is expected to have 
 a period length of 226156424186320902518104893031800133178333732395566208938371914392362024959 cycles. If the chip could be operated by 1GHz this would be reached
-after 3.89*10^38 years (approximately 2.78*10^28 times the age of the universe)! 
+after 3.89 10^38 years (approximately 2.78 10^28 times the age of the universe)! 
 
 The SpinalHDL based version (including more info about ASGs) can be found at https://github.com/SteffenReith/ASG
 
+Used connection polynoms:
+
+  private val connPolyStrR1 = "x^31+x^3+1"
+  private val connPolyStrR2 = "x^63+x+1"
+  private val connPolyStrR3 = "x^89+x^38+1"
+
 ## How to test
 
 Simply load the registers R1 (loadit==1), R2 (loadit == 2) and R3 (loadit == 3) with non-null seed data. Set loadit to 0 and enable to 1. A new bit is generated 

projects/tt_um_SteffenReith_ASGTop/info.yaml

@@ -1,7 +1,7 @@
 # Tiny Tapeout project information
 project:
-  title:        "ASG"      # Project title
-  author:       "Steffen Reith"      # Your name
+  title:        "ASG"               # Project title
+  author:       "Steffen Reith"     # Your name
   discord:      "steffenreith"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "An Alternating Step Generator to generate (pseudo)random bit with huge period length"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc

projects/tt_um_SteffenReith_ASGTop/stats/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_SteffenReith_ASGTop,wokwi,flow completed,0h2m0s0ms,0h1m35s0ms,107715.4085388132,0.01795472,53857.7042694066,48.56,64.86880000000001,554.66,670,0,0,0,0,0,0,0,0,0,0,-1,-1,16499,6124,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,6971216.0,0.0,37.35,27.71,2.82,0.16,-1,55,451,46,442,0,0,0,199,3,0,0,0,3,4,0,3,189,184,6,587,225,0,328,967,2107,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_SteffenReith_ASGTop,wokwi,flow completed,0h1m58s0ms,0h1m34s0ms,107715.4085388132,0.01795472,53857.7042694066,48.56,64.86880000000001,554.65,670,0,0,0,0,0,0,0,0,0,0,-1,-1,16499,6124,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,6971216.0,0.0,37.35,27.71,2.82,0.16,-1,55,451,46,442,0,0,0,199,3,0,0,0,3,4,0,3,189,184,6,587,225,0,328,967,2107,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_SteffenReith_ASGTop/tt_um_SteffenReith_ASGTop.spef

@@ -1,6 +1,6 @@
 *SPEF "ieee 1481-1999"
 *DESIGN "tt_um_SteffenReith_ASGTop"
-*DATE "18:22:58 Wednesday April 03, 2024"
+*DATE "22:16:34 Thursday April 18, 2024"
 *VENDOR "The OpenROAD Project"
 *PROGRAM "OpenROAD"
 *VERSION "0889970d1790a2617e69f253221b8bd7626e51dc"