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Merge pull request #15 from Quarky93/xilinx_vck5000
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Various fixes
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Quarky93 authored Jun 2, 2023
2 parents 16718bf + 3a819d7 commit e27ea19
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Showing 14 changed files with 5,412 additions and 28 deletions.
2 changes: 1 addition & 1 deletion hw/shells/sqrl_cle215/xdma_gen2x4/build.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ phys_opt_design -directive ExploreWithAggressiveHoldFix
write_checkpoint ./post_route_sqrl_cle215_xdma_gen2x4.dcp
update_design -cell user_partition -black_box
lock_design -level routing
write_checkpoint -force ./abstract_warpshell_sqrl_cle215_xdma_gen3x8.dcp
write_checkpoint -force ./abstract_warpshell_sqrl_cle215_xdma_gen2x4.dcp
write_bitstream -bin_file -force ./warpshell_sqrl_cle215_gen2x4.bit
write_cfgmem -force -format mcs -interface spix4 -size 16 -loadbit "up 0x00000000 warpshell_sqrl_cle215_gen2x4.bit" -file "warpshell_sqrl_cle215_xdma_gen2x4.mcs"
# -----------------------------------------------------------------------------
4 changes: 2 additions & 2 deletions hw/shells/xilinx_u250/xdma_gen3x8/build.tcl
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set script_path [file dirname [file normalize [info script]]]

create_project -part xcu250-figd2104-2-e synth synth
create_project -part xcu250-figd2104-2L-e synth synth
set_property source_mgmt_mode All [current_project]

# -- [READ FILES] -------------------------------------------------------------
Expand Down Expand Up @@ -38,5 +38,5 @@ phys_opt_design -directive ExploreWithAggressiveHoldFix
write_checkpoint ./post_route_xilinx_u250_xdma_gen3x8.dcp
write_bitstream -bin_file -force ./warpshell_xilinx_u250_xdma_gen3x8.bit
write_abstract_shell -cell user_partition -force ./abstract_warpshell_xilinx_u250_xdma_gen3x8.dcp
write_cfgmem -force -format mcs -interface spix4 -size 128 -loadbit "up 0x01002000 warpshell_xilinx_u250_xdma_gen3x8.bit" -file "warpshell_xilinx_u250_xdma_gen3x8.mcs"
write_cfgmem -force -format mcs -interface spix4 -size 256 -loadbit "up 0x01002000 warpshell_xilinx_u250_xdma_gen3x8.bit" -file "warpshell_xilinx_u250_xdma_gen3x8.mcs"
# -----------------------------------------------------------------------------
2 changes: 1 addition & 1 deletion hw/shells/xilinx_u250/xdma_gen3x8/edit.tcl
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set script_path [file dirname [file normalize [info script]]]

create_project -in_memory -part xcu250-figd2104-2-e
create_project -in_memory -part xcu250-figd2104-2L-e
set_property source_mgmt_mode All [current_project]

proc commit {} {
Expand Down
22 changes: 11 additions & 11 deletions hw/shells/xilinx_u250/xdma_gen3x8/shell.bd
Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
{
"design": {
"design_info": {
"boundary_crc": "0x2C264B02CCACC96",
"device": "xcu250-figd2104-2-e",
"boundary_crc": "0x2C264B07000CB52",
"device": "xcu250-figd2104-2L-e",
"name": "shell",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "None",
"tool_version": "2022.2",
"tool_version": "2023.1",
"validated": "true"
},
"design_tree": {
Expand Down Expand Up @@ -205,7 +205,7 @@
},
"HAS_CACHE": {
"value": "0",
"value_src": "default"
"value_src": "ip_prop"
},
"HAS_LOCK": {
"value": "0"
Expand All @@ -216,7 +216,7 @@
},
"HAS_QOS": {
"value": "0",
"value_src": "default"
"value_src": "ip_prop"
},
"HAS_REGION": {
"value": "0",
Expand Down Expand Up @@ -276,7 +276,7 @@
"value_src": "ip_prop"
},
"SUPPORTS_NARROW_BURST": {
"value": "0",
"value": "1",
"value_src": "default_prop"
},
"WUSER_BITS_PER_BYTE": {
Expand Down Expand Up @@ -496,7 +496,7 @@
"value_src": "ip_prop"
},
"SUPPORTS_NARROW_BURST": {
"value": "0",
"value": "1",
"value_src": "default_prop"
},
"WUSER_BITS_PER_BYTE": {
Expand Down Expand Up @@ -1336,14 +1336,14 @@
},
"m00_couplers_to_axi_interconnect_dma": {
"interface_ports": [
"M00_AXI",
"m00_couplers/M_AXI"
"m00_couplers/M_AXI",
"M00_AXI"
]
},
"m01_couplers_to_axi_interconnect_dma": {
"interface_ports": [
"M01_AXI",
"m01_couplers/M_AXI"
"m01_couplers/M_AXI",
"M01_AXI"
]
},
"s00_couplers_to_xbar": {
Expand Down
10 changes: 5 additions & 5 deletions hw/shells/xilinx_u250/xdma_gen3x8/user.bd
Original file line number Diff line number Diff line change
Expand Up @@ -2,11 +2,11 @@
"design": {
"design_info": {
"boundary_crc": "0x9F0EE1D921DEB20C",
"device": "xcu250-figd2104-2-e",
"device": "xcu250-figd2104-2L-e",
"name": "user",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "None",
"tool_version": "2022.2",
"tool_version": "2023.1",
"validated": "true"
},
"design_tree": {
Expand Down Expand Up @@ -771,8 +771,8 @@
},
"smartconnect_dma": {
"vlnv": "xilinx.com:ip:smartconnect:1.0",
"xci_name": "user_smartconnect_0_0",
"xci_path": "ip/user_smartconnect_0_0/user_smartconnect_0_0.xci",
"xci_name": "user_smartconnect_dma_0",
"xci_path": "ip/user_smartconnect_dma_0/user_smartconnect_dma_0.xci",
"inst_hier_path": "smartconnect_dma",
"parameters": {
"NUM_SI": {
Expand Down Expand Up @@ -922,7 +922,7 @@
"SEG_dummy_dma_target_Mem0": {
"address_block": "/dummy_dma_target/S_AXI/Mem0",
"offset": "0x0000000000000000",
"range": "256T"
"range": "8K"
}
}
}
Expand Down
19 changes: 11 additions & 8 deletions hw/shells/xilinx_u55n/xdma_gen3x8/shell.bd
Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
{
"design": {
"design_info": {
"boundary_crc": "0x7BC4BA6E561CA014",
"boundary_crc": "0x7BC4BA6E0DE2C31A",
"device": "xcu55n-fsvh2892-2L-e",
"name": "shell",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "None",
"tool_version": "2022.2",
"tool_version": "2023.1",
"validated": "true"
},
"design_tree": {
Expand Down Expand Up @@ -237,7 +237,7 @@
"value_src": "ip_prop"
},
"SUPPORTS_NARROW_BURST": {
"value": "1",
"value": "0",
"value_src": "default_prop"
},
"WUSER_BITS_PER_BYTE": {
Expand Down Expand Up @@ -539,7 +539,7 @@
"value_src": "ip_prop"
},
"SUPPORTS_NARROW_BURST": {
"value": "1",
"value": "0",
"value_src": "default_prop"
},
"WUSER_BITS_PER_BYTE": {
Expand Down Expand Up @@ -1898,6 +1898,9 @@
"pf0_base_class_menu": {
"value": "Processing_accelerators"
},
"pf0_subsystem_id": {
"value": "A001"
},
"pl_link_cap_max_link_speed": {
"value": "8.0_GT/s"
},
Expand Down Expand Up @@ -2292,14 +2295,14 @@
},
"m00_couplers_to_axi_interconnect_dma": {
"interface_ports": [
"M00_AXI",
"m00_couplers/M_AXI"
"m00_couplers/M_AXI",
"M00_AXI"
]
},
"m01_couplers_to_axi_interconnect_dma": {
"interface_ports": [
"M01_AXI",
"m01_couplers/M_AXI"
"m01_couplers/M_AXI",
"M01_AXI"
]
},
"s00_couplers_to_xbar": {
Expand Down
44 changes: 44 additions & 0 deletions hw/shells/xilinx_vck5000/xdma_gen4x8/build.tcl
Original file line number Diff line number Diff line change
@@ -0,0 +1,44 @@
set script_path [file dirname [file normalize [info script]]]

create_project -part xcvc1902-vsvd1760-2MP-e-S synth synth
set_property source_mgmt_mode All [current_project]

# -- [READ FILES] -------------------------------------------------------------
import_files ${script_path}/shell.bd
import_files ${script_path}/user.bd
import_files "${script_path}/io.xdc"
import_files "${script_path}/misc.xdc"
import_files "${script_path}/floorplan.xdc"
import_files "${script_path}/top.v"
# -----------------------------------------------------------------------------

# -- [GENERATE BDS] -----------------------------------------------------------
set_property synth_checkpoint_mode Hierarchical [get_files shell.bd]
set_property synth_checkpoint_mode Hierarchical [get_files user.bd]
generate_target all [get_files shell.bd]
generate_target all [get_files user.bd]
# -----------------------------------------------------------------------------

# -- [COMPILE] ----------------------------------------------------------------
export_ip_user_files -of_objects [get_files shell.bd] -no_script -sync -force -quiet
export_ip_user_files -of_objects [get_files user.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] shell.bd]
create_ip_run [get_files -of_objects [get_fileset sources_1] user.bd]

launch_runs synth_1 -jobs 16
wait_on_runs synth_1

open_run synth_1
write_checkpoint -force ./post_synth_xilinx_vck5000_xdma_gen4x8.dcp
opt_design -directive Explore
place_design -directive Auto_1
phys_opt_design -directive ExploreWithAggressiveHoldFix
route_design -directive AggressiveExplore
phys_opt_design -directive ExploreWithAggressiveHoldFix
write_checkpoint ./post_route_xilinx_vck5000_xdma_gen4x8.dcp
write_device_image -force ./warpshell_xilinx_vck5000_xdma_gen4x8.pdi
update_design -cell user_partition -black_box
lock_design -level routing
write_checkpoint -force ./abstract_warpshell_xilinx_vck5000_xdma_gen4x8.dcp
# write_cfgmem -force -format mcs -interface spix4 -size 128 -loadbit "up 0x01002000 warpshell_xilinx_vck5000_xdma_gen4x8.bit" -file "warpshell_xilinx_vck5000_xdma_gen4x8.mcs"
# -----------------------------------------------------------------------------
21 changes: 21 additions & 0 deletions hw/shells/xilinx_vck5000/xdma_gen4x8/edit.tcl
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
set script_path [file dirname [file normalize [info script]]]

create_project -in_memory -part xcvc1902-vsvd1760-2MP-e-S
set_property source_mgmt_mode All [current_project]

proc commit {} {
validate_bd_design
save_bd_design
set bd [current_bd_design]
puts "Writing to: $::script_path/${bd}.bd"
file copy -force ./${bd}/${bd}.bd $::script_path/
}

file mkdir ./shell/
file mkdir ./user/
file copy ${script_path}/shell.bd ./shell/shell.bd
file copy ${script_path}/user.bd ./user/user.bd
read_bd ./shell/shell.bd
read_bd ./user/user.bd

start_gui
4 changes: 4 additions & 0 deletions hw/shells/xilinx_vck5000/xdma_gen4x8/floorplan.xdc
Original file line number Diff line number Diff line change
@@ -0,0 +1,4 @@
create_pblock user_partition
add_cells_to_pblock user_partition [get_cells user_partition]
resize_pblock [get_pblocks user_partition] -add {CLOCKREGION_X0Y4:CLOCKREGION_X9Y5 CLOCKREGION_X1Y3:CLOCKREGION_X9Y3 CLOCKREGION_X2Y1:CLOCKREGION_X9Y2}
set_property HD.RECONFIGURABLE TRUE [get_cells user_partition]
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