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cpu-o3: fix a memory leak problem #274

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Jan 23, 2025
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1 change: 0 additions & 1 deletion src/cpu/o3/lsq.cc
Original file line number Diff line number Diff line change
Expand Up @@ -633,7 +633,6 @@ LSQ::recvFunctionalCustomSignal(PacketPtr pkt, int sig)
it++;
}
}
delete pkt;
panic_if(bus.size() > getLQEntries(), "elements on bus should never be greater than LQ size");
} else {
panic("unsupported sig %d in recvFunctionalCustomSignal\n", sig);
Expand Down
22 changes: 14 additions & 8 deletions src/mem/cache/base.cc
Original file line number Diff line number Diff line change
Expand Up @@ -93,16 +93,19 @@ BaseCache::SendTimingRespEvent::description() const
return "BaseCache response event";
}

BaseCache::SendCustomEvent::SendCustomEvent(BaseCache* cache, PacketPtr pkt, int sig)
BaseCache::SendCustomEvent::SendCustomEvent(BaseCache* cache, PacketPtr pkt, int sig, bool deletePkt)
: Event(Stat_Event_Pri, AutoDelete),
cache(cache),
pkt(pkt),
sig(sig) {}
sig(sig),
deletePkt(deletePkt) {}

void
BaseCache::SendCustomEvent::process()
{
cache->cpuSidePort.sendCustomSignal(pkt, sig);
if (deletePkt)
delete pkt;
}

const char*
Expand Down Expand Up @@ -2051,14 +2054,17 @@ BaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
pkt->payloadDelay);

// NOTE: just send the block address back to lsu
// NOTE: Dcache sends the block address back to lsu
// notify lsu to clear data on data bus
// when the block is ready in dcache (load can get data from cache directly)
PacketPtr customPkt = new Packet(pkt->req, MemCmd::CustomBusClear);
customPkt->setAddr(addr);
SendCustomEvent* clearEvent = new SendCustomEvent(this, customPkt, DcacheRespType::Bus_Clear);
schedule(clearEvent, clockEdge(fillLatency) + pkt->headerDelay +
pkt->payloadDelay);
if (cacheLevel == 1 && !isReadOnly) {
PacketPtr customPkt = new Packet(pkt->req, MemCmd::CustomBusClear);
customPkt->setAddr(addr);
// set `deletePkt` as true to ensure that the customPkt will be deleted finally.
SendCustomEvent* clearEvent = new SendCustomEvent(this, customPkt, DcacheRespType::Bus_Clear, true);
schedule(clearEvent, clockEdge(fillLatency) + pkt->headerDelay +
pkt->payloadDelay);
}

Request::XsMetadata blk_meta = blk->getXsMetadata();
blk_meta.prefetchSource = pkt->req->getPFSource();
Expand Down
3 changes: 2 additions & 1 deletion src/mem/cache/base.hh
Original file line number Diff line number Diff line change
Expand Up @@ -365,8 +365,9 @@ class BaseCache : public ClockedObject, CacheAccessor
BaseCache* cache;
PacketPtr pkt;
int sig;
bool deletePkt;
public:
SendCustomEvent(BaseCache* cache, PacketPtr pkt, int sig);
SendCustomEvent(BaseCache* cache, PacketPtr pkt, int sig, bool deletePkt);
void process() override;
const char* description() const override;
};
Expand Down
3 changes: 2 additions & 1 deletion src/mem/cache/cache.cc
Original file line number Diff line number Diff line change
Expand Up @@ -990,7 +990,8 @@ Cache::sendHintViaMSHRTargets(MSHR *mshr, const PacketPtr pkt)
if (sendHintTime == curTick()) {
BaseCache::cpuSidePort.sendCustomSignal(tgt_pkt, DcacheRespType::Hint);
} else {
SendCustomEvent* hintEvent = new SendCustomEvent(this, tgt_pkt, DcacheRespType::Hint);
// set `deletePkt` as false because tgt_pkt should not be deleted by Hint event.
SendCustomEvent* hintEvent = new SendCustomEvent(this, tgt_pkt, DcacheRespType::Hint, false);
schedule(hintEvent, sendHintTime);
}
firstTgt = false;
Expand Down