slice stall and dcache write stall #264
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happy-lx
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Jan 9, 2025
happy-lx
reviewed
Jan 9, 2025
| // write request will stall one cycle | ||
| // so 2 cycle send one write request | ||
| if (lsq->getDcacheWriteStall()) { | ||
| lsq->setDcacheWriteStall(false); | ||
| return; |
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The Dcache requeset of this store may write DataSram after N cycles (4 if Hit, 10+/100+ if miss) arriving at Dcache, (I feel that the blocking should be done at that time instead of blocking directly in the next cycle?
Change-Id: I58448dc970fa56cb0fca5b34bd15a990b8e57799
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Change-Id: Iafccda7d47bce2a2fe6fbe37b8fc84dc8cde1c2b
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