cpu-o3: write request will block dcache one cycle

Change-Id: Iafccda7d47bce2a2fe6fbe37b8fc84dc8cde1c2b
OpenXiangShan · Jan 13, 2025 · 449ae92 · 449ae92
1 parent d6062b9
commit 449ae92
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Showing 3 changed files with 18 additions and 5 deletions.
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
@@ -208,6 +208,9 @@ LSQ::clearAddresses(Tick time)
 bool
 LSQ::bankConflictedCheck(Addr vaddr)
 {
+    if (dcacheWriteStall) {
+        return true;
+    }
     bool now_bank_conflict = false;
     // 64KB Dcache 8way 128sets
     // [12:6]   [5:3]     [2:0]

diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
@@ -950,6 +950,10 @@ class LSQ
 
     bool bankConflictedCheck(Addr vaddr);
 
+    void setDcacheWriteStall(bool stall) { dcacheWriteStall = stall; }
+
+    bool getDcacheWriteStall() { return dcacheWriteStall; }
+
     /** Is D-cache blocked? */
     bool cacheBlocked() const;
     /** Set D-cache blocked status */
@@ -975,6 +979,7 @@ class LSQ
 
     Tick lastConflictCheckTick;
 
+    bool dcacheWriteStall = false;
     std::vector<int64_t> l1dBankAddresses;
     struct NullStruct {};
     boost::compute::detail::lru_cache<uint64_t, NullStruct> recentlyloadAddr;

diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
@@ -1404,16 +1404,20 @@ bool LSQUnit::insertStoreBuffer(Addr vaddr, Addr paddr, uint8_t* datas, uint64_t
 void
 LSQUnit::storeBufferEvictToCache()
 {
-    if (isStoreBlocked) {
-        return;
-    }
-    if (storeBuffer.size() == 0) {
+    if (storeBufferFlushing && storeBuffer.size() == 0) [[unlikely]] {
         assert(storeBuffer.unsentSize() == 0);
         storeBufferFlushing = false;
         cpu->activityThisCycle();
+    }
+
+    // write request will stall one cycle
+    // so 2 cycle send one write request
+    if (lsq->getDcacheWriteStall()) {
+        lsq->setDcacheWriteStall(false);
         return;
     }
-    if (storeBuffer.unsentSize() == 0) {
+
+    if (isStoreBlocked || storeBuffer.unsentSize() == 0) {
         return;
     }
 
@@ -1470,6 +1474,7 @@ LSQUnit::storeBufferEvictToCache()
         }
         DPRINTF(StoreBuffer, "send packet successed\n");
         entry->sending = true;
+        lsq->setDcacheWriteStall(true);
         storeBufferWritebackInactive = 0;
     } else {
         // Timeout