drivers: uart: nrfx_uarte: Major rework of the legacy UART shim to allow using it for nrf54x

boards/nordic/nrf54h20dk/Kconfig.defconfig

@@ -14,3 +14,11 @@ config BT_CTLR
 	default y if BT
 
 endif # BOARD_NRF54H20DK_NRF54H20_CPURAD
+
+if BOARD_NRF54H20DK_NRF54H20_CPUPPR
+
+# As PPR has limited memory most of tests does not fit with asserts enabled.
+config ASSERT
+	default n
+
+endif # BOARD_NRF54H20DK_NRF54H20_CPUPPR

drivers/serial/Kconfig.nrfx

@@ -31,12 +31,20 @@ config UART_NRFX_UARTE
 config UART_NRFX_UARTE_LEGACY_SHIM
 	bool "Legacy UARTE shim"
 	depends on UART_NRFX_UARTE
-	depends on !SOC_SERIES_NRF54LX
-	depends on !SOC_SERIES_NRF54HX || RISCV
-	depends on !SOC_SERIES_NRF92X || RISCV
-	# New shim takes more ROM. Until it is fixed use legacy shim.
 	default y
 
+config UART_NRFX_UARTE_ENHANCED_RX
+	bool "Enhanced RX handling"
+	depends on UART_ASYNC_API
+	depends on UART_NRFX_UARTE_LEGACY_SHIM
+	default y if !(UART_0_NRF_HW_ASYNC || UART_1_NRF_HW_ASYNC || UART_2_NRF_HW_ASYNC)
+	help
+	  Enable RX handling mode which is switching buffers on timeout. This is an
+	  enhancement compared to other two modes (default and hardware assisted).
+	  Default mode could miscount bytes when interrupt was not handled on time
+	  and hardware assisted required TIMER peripheral instance and PPI channel
+	  for accurate byte counting.
+
 config UART_ASYNC_TX_CACHE_SIZE
 	int "TX cache buffer size"
 	depends on UART_ASYNC_API
@@ -47,6 +55,16 @@ config UART_ASYNC_TX_CACHE_SIZE
 	  in RAM, because EasyDMA in UARTE peripherals can only transfer data
 	  from RAM.
 
+config UART_NRFX_UARTE_RX_FLUSH_MAGIC_BYTE
+	int "Byte used for RX FIFO flush workaround"
+	default 171
+	range 0 255
+	help
+	  Byte used to fill the buffer before RX FIFO is flushed into it. Due to the
+	  HW anomaly a workaround need to be applied which checks if content of the
+	  buffer changed. There are cases when specific value of the magic byte is
+	  used if it is known that certain bytes are less likely to occur.
+
 if HAS_HW_NRF_UART0 || HAS_HW_NRF_UARTE0
 nrfx_uart_num = 0
 rsource "Kconfig.nrfx_uart_instance"

drivers/serial/Kconfig.nrfx_uart_instance

@@ -68,6 +68,8 @@ config UART_$(nrfx_uart_num)_NRF_ASYNC_LOW_POWER
 	depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
 	depends on UART_ASYNC_API
 	depends on UART_NRFX_UARTE_LEGACY_SHIM
+	depends on !PM_DEVICE
+	default y
 	help
 	  When enabled, UARTE is enabled before each TX or RX usage and disabled
 	  when not used. Disabling UARTE while in idle allows to achieve lowest
@@ -119,12 +121,3 @@ config UART_$(nrfx_uart_num)_A2I_RX_BUF_COUNT
 	default 0
 	help
 	  Number of chunks into RX space is divided.
-
-config UART_$(nrfx_uart_num)_GPIO_MANAGEMENT
-	bool "GPIO management on port $(nrfx_uart_num)"
-	depends on PM_DEVICE
-	default y
-	help
-	  If enabled, the driver will configure the GPIOs used by the uart to
-	  their default configuration when device is powered down. The GPIOs
-	  will be configured back to correct state when UART is powered up.

drivers/serial/uart_nrfx_uart.c

@@ -1086,12 +1086,9 @@ static int uart_nrfx_pm_action(const struct device *dev,
 
 	switch (action) {
 	case PM_DEVICE_ACTION_RESUME:
-		if (IS_ENABLED(CONFIG_UART_0_GPIO_MANAGEMENT)) {
-			ret = pinctrl_apply_state(config->pcfg,
-						  PINCTRL_STATE_DEFAULT);
-			if (ret < 0) {
-				return ret;
-			}
+		ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+		if (ret < 0) {
+			return ret;
 		}
 
 		nrf_uart_enable(uart0_addr);
@@ -1102,13 +1099,9 @@ static int uart_nrfx_pm_action(const struct device *dev,
 		break;
 	case PM_DEVICE_ACTION_SUSPEND:
 		nrf_uart_disable(uart0_addr);
-
-		if (IS_ENABLED(CONFIG_UART_0_GPIO_MANAGEMENT)) {
-			ret = pinctrl_apply_state(config->pcfg,
-						  PINCTRL_STATE_SLEEP);
-			if (ret < 0) {
-				return ret;
-			}
+		ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
+		if (ret < 0) {
+			return ret;
 		}
 		break;
 	default: