core: Implement dialect attribute opaque syntax. (#1726)

Implement the dialect attribute opaque syntax, i.e., `#arith<fastmath<none>>` Adds an OpaqueSyntaxAttribute simple class to inherit from on Attributes meant to be printed using that syntax, just like TypeAttribute for using `!` instead of `#` More MLIR compliancy! --------- Co-authored-by: Mathieu Fehr <[email protected]>
xdslproject · Nov 6, 2023 · 95a7d1f · 95a7d1f
1 parent 8f925a7
commit 95a7d1f
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diff --git a/docs/irdl.ipynb b/docs/irdl.ipynb
@@ -233,7 +233,7 @@
      "name": "stdout",
      "output_type": "stream",
      "text": [
-      "#int<3> should be of base attribute string\n"
+      "#builtin.int<3> should be of base attribute string\n"
      ]
     }
    ],
@@ -588,7 +588,7 @@
      "name": "stdout",
      "output_type": "stream",
      "text": [
-      "\"ga\" should be of base attribute int\n"
+      "\"ga\" should be of base attribute builtin.int\n"
      ]
     }
    ],
@@ -694,7 +694,7 @@
      "output_type": "stream",
      "text": [
       "In integer_type attribute verifier: 1 parameters expected, got 2\n",
-      "\"ga\" should be of base attribute int\n"
+      "\"ga\" should be of base attribute builtin.int\n"
      ]
     }
    ],
@@ -1381,7 +1381,7 @@
      "name": "stdout",
      "output_type": "stream",
      "text": [
-      "\"string_attr_op\"() {\"value\" = \"ga\", \"other_attr\" = #int<42>} : () -> ()"
+      "\"string_attr_op\"() {\"value\" = \"ga\", \"other_attr\" = #builtin.int<42>} : () -> ()"
      ]
     }
    ],

diff --git a/docs/tutorial.ipynb b/docs/tutorial.ipynb
@@ -156,7 +156,7 @@
      "name": "stdout",
      "output_type": "stream",
      "text": [
-      "#int<42>"
+      "#builtin.int<42>"
      ]
     }
    ],
@@ -246,7 +246,7 @@
      "name": "stdout",
      "output_type": "stream",
      "text": [
-      "#int<64>"
+      "#builtin.int<64>"
      ]
     }
    ],

diff --git a/tests/dialects/test_builtin.py b/tests/dialects/test_builtin.py
@@ -309,7 +309,7 @@ def verify(
         context = getattr(e, "__context__")
         assert "fail" in context
 
-    with pytest.raises(VerifyException, match="wrapped #int<1>") as e:
+    with pytest.raises(VerifyException, match="wrapped #builtin.int<1>") as e:
         outer = CustomErrorMessageAttrConstraint(inner, lambda k: f"wrapped {k}")
         outer.verify(one, {})
         assert hasattr(e, "__context__")

diff --git a/tests/dialects/test_gpu.py b/tests/dialects/test_gpu.py
@@ -3,7 +3,7 @@
 from xdsl.dialects.gpu import (
     AllocOp,
     AllReduceOp,
-    AllReduceOperationAttr,
+    AllReduceOpAttr,
     AsyncTokenType,
     BarrierOp,
     BlockDimOp,
@@ -34,7 +34,7 @@
 
 
 def test_dimension():
-    dim = DimensionAttr.from_dimension("x")
+    dim = DimensionAttr("x")
 
     assert dim.data == "x"
 
@@ -79,13 +79,13 @@ def test_alloc():
 
 
 def test_all_reduce_operation():
-    op = AllReduceOperationAttr.from_op("add")
+    op = AllReduceOpAttr("add")
 
     assert op.data == "add"
 
 
 def test_all_reduce():
-    op = AllReduceOperationAttr.from_op("add")
+    op = AllReduceOpAttr("add")
 
     init = arith.Constant.from_int_and_width(0, builtin.IndexType())
 
@@ -120,7 +120,7 @@ def test_barrier():
 
 
 def test_block_dim():
-    dim = DimensionAttr.from_dimension("x")
+    dim = DimensionAttr("x")
 
     block_dim = BlockDimOp(dim)
 
@@ -129,7 +129,7 @@ def test_block_dim():
 
 
 def test_block_id():
-    dim = DimensionAttr.from_dimension("x")
+    dim = DimensionAttr("x")
 
     block_id = BlockIdOp(dim)
 
@@ -181,7 +181,7 @@ def test_gpu_module_end():
 
 
 def test_global_id():
-    dim = DimensionAttr.from_dimension("x")
+    dim = DimensionAttr("x")
 
     global_id = GlobalIdOp(dim)
 
@@ -190,7 +190,7 @@ def test_global_id():
 
 
 def test_grid_dim():
-    dim = DimensionAttr.from_dimension("x")
+    dim = DimensionAttr("x")
 
     grid_dim = GridDimOp(dim)
 
@@ -395,7 +395,7 @@ def test_subgroup_size():
 
 
 def test_thread_id():
-    dim = DimensionAttr.from_dimension("x")
+    dim = DimensionAttr("x")
 
     thread_id = ThreadIdOp(dim)
 

diff --git a/tests/filecheck/dialects/arith/arith_attrs.mlir b/tests/filecheck/dialects/arith/arith_attrs.mlir
@@ -4,7 +4,8 @@
 
   "test.op"() {attrs = [
                   #arith.fastmath<reassoc>,
-                  // CHECK: #arith.fastmath<reassoc>
+                  #arith<fastmath<reassoc>>,
+                  // CHECK: #arith.fastmath<reassoc>, #arith.fastmath<reassoc>
                   #arith.fastmath<nnan>,
                   // CHECK-SAME: #arith.fastmath<nnan>
                   #arith.fastmath<ninf>,

diff --git a/tests/filecheck/dialects/builtin/attrs.mlir b/tests/filecheck/dialects/builtin/attrs.mlir
@@ -19,12 +19,12 @@
     %x7 = "arith.constant"() {"value" = 0 : i64, "test" = array<i32: 2, 3, 4>} : () -> i64
     // CHECK:  "test" = array<f32: 2.1, 3.2, 4.3>
     %x8 = "arith.constant"() {"value" = 0 : i64, "test" = array<f32: 2.1, 3.2, 4.3>} : () -> i64
-    // CHECK:  "test" = #signedness<signless>
-    %x9 = "arith.constant"() {"value" = 0 : i64, "test" = #signedness<signless>} : () -> i64
-    // CHECK:  "test" = #signedness<signed>
-    %x10 = "arith.constant"() {"value" = 0 : i64, "test" = #signedness<signed>} : () -> i64
-    // CHECK:  "test" = #signedness<unsigned>
-    %x11 = "arith.constant"() {"value" = 0 : i64, "test" = #signedness<unsigned>} : () -> i64
+    // CHECK:  "test" = #builtin.signedness<signless>
+    %x9 = "arith.constant"() {"value" = 0 : i64, "test" = #builtin.signedness<signless>} : () -> i64
+    // CHECK:  "test" = #builtin.signedness<signed>
+    %x10 = "arith.constant"() {"value" = 0 : i64, "test" = #builtin.signedness<signed>} : () -> i64
+    // CHECK:  "test" = #builtin.signedness<unsigned>
+    %x11 = "arith.constant"() {"value" = 0 : i64, "test" = #builtin.signedness<unsigned>} : () -> i64
     // CHECK:  "test" = @foo
     %x12 = "arith.constant"() {"value" = 0 : i64, "test" = @foo} : () -> i64
     // CHECK:  "test" = @foo::@bar

diff --git a/tests/filecheck/dialects/builtin/dense_array_invalid_element.mlir b/tests/filecheck/dialects/builtin/dense_array_invalid_element.mlir
@@ -1,6 +1,6 @@
 // RUN: xdsl-opt %s --parsing-diagnostics | filecheck %s
 
-"builtin.module" () {"test" = array<!fun<[],[]>: 2, 5, 2>} ({
+"builtin.module" () {"test" = array<()->(): 2, 5, 2>} ({
 })
 
 // CHECK: dense array element type must be an integer or floating point type
diff --git a/tests/filecheck/dialects/gpu/invalid.mlir b/tests/filecheck/dialects/gpu/invalid.mlir
@@ -19,7 +19,7 @@
 "builtin.module"() ({
 }) {"wrong_all_reduce_operation" = #gpu<all_reduce_op magic>}: () -> ()
 
-// CHECK: Unexpected op magic. A gpu all_reduce_op can only be add, and, max, min, mul, or, or xor
+// CHECK: Expected add, and, max, min, mul, or, or xor.
 
 // -----
 
@@ -77,7 +77,7 @@
 "builtin.module"() ({
 }) {"wrong_dim" = #gpu<dim w>}: () -> ()
 
-// CHECK: Unexpected dim w. A gpu dim can only be x, y, or z
+// CHECK: Expected x, y or z.
 
 // -----
 

diff --git a/tests/filecheck/dialects/riscv_snitch/ops.mlir b/tests/filecheck/dialects/riscv_snitch/ops.mlir
@@ -37,10 +37,10 @@ riscv_func.func @main() {
 // CHECK-GENERIC-NEXT:     %scfgwi_zero = "riscv_snitch.scfgwi"(%0) {"immediate" = 42 : si12} : (!riscv.reg<>) -> !riscv.reg<zero>
 // CHECK-GENERIC-NEXT:    "riscv_snitch.frep_outer"(%{{.*}}) ({
 // CHECK-GENERIC-NEXT:      %{{.*}} = "riscv.add"(%{{.*}}, %{{.*}}) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<>
-// CHECK-GENERIC-NEXT:    }) {"stagger_mask" = #int<0>, "stagger_count" = #int<0>} : (!riscv.reg<>) -> ()
+// CHECK-GENERIC-NEXT:    }) {"stagger_mask" = #builtin.int<0>, "stagger_count" = #builtin.int<0>} : (!riscv.reg<>) -> ()
 // CHECK-GENERIC-NEXT:    "riscv_snitch.frep_inner"(%{{.*}}) ({
 // CHECK-GENERIC-NEXT:      %{{.*}} = "riscv.add"(%{{.*}}, %{{.*}}) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<>
-// CHECK-GENERIC-NEXT:    }) {"stagger_mask" = #int<0>, "stagger_count" = #int<0>} : (!riscv.reg<>) -> ()
+// CHECK-GENERIC-NEXT:    }) {"stagger_mask" = #builtin.int<0>, "stagger_count" = #builtin.int<0>} : (!riscv.reg<>) -> ()
 // CHECK-GENERIC-NEXT:     "riscv_func.return"() : () -> ()
 // CHECK-GENERIC-NEXT:   }) {"sym_name" = "main", "function_type" = () -> ()} : () -> ()
 // CHECK-GENERIC-NEXT: }) : () -> ()
diff --git a/tests/filecheck/dialects/snitch/snitch_ops.mlir b/tests/filecheck/dialects/snitch/snitch_ops.mlir
@@ -5,16 +5,16 @@
   %stride = "test.op"() : () -> !riscv.reg<>
   %rep = "test.op"() : () -> !riscv.reg<>
   // Usual SSR setup sequence:
-  "snitch.ssr_set_dimension_bound"(%bound) {"dm" = #int<0>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
-  // CHECK: "snitch.ssr_set_dimension_bound"(%bound) {"dm" = #int<0>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
-  "snitch.ssr_set_dimension_stride"(%stride) {"dm" = #int<0>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
-  // CHECK: "snitch.ssr_set_dimension_stride"(%stride) {"dm" = #int<0>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
-  "snitch.ssr_set_dimension_source"(%addr) {"dm" = #int<0>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
-  // CHECK: "snitch.ssr_set_dimension_source"(%addr) {"dm" = #int<0>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
-  "snitch.ssr_set_dimension_destination"(%addr) {"dm" = #int<0>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
-  // CHECK: "snitch.ssr_set_dimension_destination"(%addr) {"dm" = #int<0>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
-  "snitch.ssr_set_stream_repetition"(%rep) {"dm" = #int<0>} : (!riscv.reg<>) -> ()
-  // CHECK: "snitch.ssr_set_stream_repetition"(%rep) {"dm" = #int<0>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_dimension_bound"(%bound) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
+  // CHECK: "snitch.ssr_set_dimension_bound"(%bound) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_dimension_stride"(%stride) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
+  // CHECK: "snitch.ssr_set_dimension_stride"(%stride) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_dimension_source"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
+  // CHECK: "snitch.ssr_set_dimension_source"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_dimension_destination"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
+  // CHECK: "snitch.ssr_set_dimension_destination"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_stream_repetition"(%rep) {"dm" = #builtin.int<0>} : (!riscv.reg<>) -> ()
+  // CHECK: "snitch.ssr_set_stream_repetition"(%rep) {"dm" = #builtin.int<0>} : (!riscv.reg<>) -> ()
   "snitch.ssr_enable"() : () -> ()
   // CHECK-NEXT: "snitch.ssr_enable"() : () -> ()
   "snitch.ssr_disable"() : () -> ()

diff --git a/tests/filecheck/dialects/snitch/snitch_to_riscv_lowering.mlir b/tests/filecheck/dialects/snitch/snitch_to_riscv_lowering.mlir
@@ -5,32 +5,32 @@ builtin.module {
   %stride = riscv.li 4 : () -> !riscv.reg<>
   %rep = riscv.li 0 : () -> !riscv.reg<>
   // SSR setup sequence for dimension 0
-  "snitch.ssr_set_dimension_bound"(%bound) {"dm" = #int<0>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_dimension_bound"(%bound) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
   // CHECK: %{{.*}} = riscv.li 64 : () -> !riscv.reg<>
   // CHECK-NEXT: %{{.*}} = riscv_snitch.scfgw %bound, %{{.*}} : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<zero>
-  "snitch.ssr_set_dimension_stride"(%stride) {"dm" = #int<0>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_dimension_stride"(%stride) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
   // CHECK: %{{.*}} = riscv.li 192 : () -> !riscv.reg<>
   // CHECK-NEXT: %{{.*}} riscv_snitch.scfgw %stride, %{{.*}} : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<zero>
-  "snitch.ssr_set_dimension_source"(%addr) {"dm" = #int<0>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_dimension_source"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
   // CHECK: %{{.*}} = riscv.li 768 : () -> !riscv.reg<>
   // %{{.*}} = riscv_snitch.scfgw %addr, %{{.*}} : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<zero>
-  "snitch.ssr_set_dimension_destination"(%addr) {"dm" = #int<0>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_dimension_destination"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
   // CHECK: %{{.*}} = riscv.li 896 : () -> !riscv.reg<>
   // CHECK-NEXT: %{{.*}} = riscv_snitch.scfgw %addr, %{{.*}} : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<zero>
   // SSR setup sequence for dimension 3
-  "snitch.ssr_set_dimension_bound"(%bound) {"dm" = #int<0>, "dimension" = #int<3>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_dimension_bound"(%bound) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<3>} : (!riscv.reg<>) -> ()
   // CHECK: %{{.*}} = riscv.li 160 : () -> !riscv.reg<>
   // CHECK-NEXT: %{{.*}} = riscv_snitch.scfgw %bound, %{{.*}} : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<zero>
-  "snitch.ssr_set_dimension_stride"(%stride) {"dm" = #int<0>, "dimension" = #int<3>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_dimension_stride"(%stride) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<3>} : (!riscv.reg<>) -> ()
   // CHECK: %{{.*}} = riscv.li 288 : () -> !riscv.reg<>
   // CHECK-NEXT: %{{.*}} = riscv_snitch.scfgw %stride, %{{.*}} : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<zero>
-  "snitch.ssr_set_dimension_source"(%addr) {"dm" = #int<0>, "dimension" = #int<3>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_dimension_source"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<3>} : (!riscv.reg<>) -> ()
   // CHECK: %{{.*}} = riscv.li 864 : () -> !riscv.reg<>
   // riscv_snitch.scfgw %addr, %{{.*}} : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<zero>
-  "snitch.ssr_set_dimension_destination"(%addr) {"dm" = #int<0>, "dimension" = #int<3>} : (!riscv.reg<>) -> ()
+  "snitch.ssr_set_dimension_destination"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<3>} : (!riscv.reg<>) -> ()
   // CHECK: %{{.*}} = riscv.li 992 : () -> !riscv.reg<>
   // CHECK-NEXT: %{{.*}} = riscv_snitch.scfgw %addr, %{{.*}} : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<zero>
-  "snitch.ssr_set_stream_repetition"(%rep) {"dm" = #int<0>}: (!riscv.reg<>) -> ()
+  "snitch.ssr_set_stream_repetition"(%rep) {"dm" = #builtin.int<0>}: (!riscv.reg<>) -> ()
   // CHECK: %{{.*}} = riscv.li 32 : () -> !riscv.reg<>
   // CHECK-NEXT: %{{.*}} = riscv_snitch.scfgw %rep, %{{.*}} : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<zero>
   // On/Off switching sequence

diff --git a/tests/filecheck/dialects/snitch_stream/convert_snitch_stream_to_snitch.mlir b/tests/filecheck/dialects/snitch_stream/convert_snitch_stream_to_snitch.mlir
@@ -5,31 +5,31 @@
 %A, %B, %C = "test.op"() : () -> (!riscv.reg<>, !riscv.reg<>, !riscv.reg<>)
 // CHECK-NEXT:  %A, %B, %C = "test.op"() : () -> (!riscv.reg<>, !riscv.reg<>, !riscv.reg<>)
 
-%0 = "snitch_stream.stride_pattern"() {"ub" = [#int<2>, #int<3>], "strides" = [#int<24>, #int<8>], "dm" = #int<31>} : () -> !snitch_stream.stride_pattern_type
+%0 = "snitch_stream.stride_pattern"() {"ub" = [#builtin.int<2>, #builtin.int<3>], "strides" = [#builtin.int<24>, #builtin.int<8>], "dm" = #builtin.int<31>} : () -> !snitch_stream.stride_pattern_type
 // CHECK-NEXT:  %0 = riscv.li 2 : () -> !riscv.reg<>
 // CHECK-NEXT:  %1 = riscv.li 3 : () -> !riscv.reg<>
 // CHECK-NEXT:  %2 = riscv.li 24 : () -> !riscv.reg<>
 // CHECK-NEXT:  %3 = riscv.li 8 : () -> !riscv.reg<>
 // CHECK-NEXT:  %4 = riscv.addi %0, -1 : (!riscv.reg<>) -> !riscv.reg<>
 // CHECK-NEXT:  %5 = riscv.addi %1, -1 : (!riscv.reg<>) -> !riscv.reg<>
-// CHECK-NEXT:  "snitch.ssr_set_dimension_bound"(%4) {"dm" = #int<31>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
-// CHECK-NEXT:  "snitch.ssr_set_dimension_bound"(%5) {"dm" = #int<31>, "dimension" = #int<1>} : (!riscv.reg<>) -> ()
-// CHECK-NEXT:  "snitch.ssr_set_dimension_stride"(%2) {"dm" = #int<31>, "dimension" = #int<0>} : (!riscv.reg<>) -> ()
+// CHECK-NEXT:  "snitch.ssr_set_dimension_bound"(%4) {"dm" = #builtin.int<31>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
+// CHECK-NEXT:  "snitch.ssr_set_dimension_bound"(%5) {"dm" = #builtin.int<31>, "dimension" = #builtin.int<1>} : (!riscv.reg<>) -> ()
+// CHECK-NEXT:  "snitch.ssr_set_dimension_stride"(%2) {"dm" = #builtin.int<31>, "dimension" = #builtin.int<0>} : (!riscv.reg<>) -> ()
 // CHECK-NEXT:  %6 = riscv.mul %4, %2 : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<>
 // CHECK-NEXT:  %7 = riscv.sub %3, %6 : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<>
-// CHECK-NEXT:  "snitch.ssr_set_dimension_stride"(%7) {"dm" = #int<31>, "dimension" = #int<1>} : (!riscv.reg<>) -> ()
+// CHECK-NEXT:  "snitch.ssr_set_dimension_stride"(%7) {"dm" = #builtin.int<31>, "dimension" = #builtin.int<1>} : (!riscv.reg<>) -> ()
 
 
-%1 = "snitch_stream.strided_read"(%A, %0) {"dm" = #int<0>, "rank" = #int<2>} : (!riscv.reg<>, !snitch_stream.stride_pattern_type) -> !stream.readable<!riscv.freg<ft0>>
-// CHECK-NEXT:  "snitch.ssr_set_dimension_source"(%A) {"dm" = #int<0>, "dimension" = #int<1>} : (!riscv.reg<>) -> ()
+%1 = "snitch_stream.strided_read"(%A, %0) {"dm" = #builtin.int<0>, "rank" = #builtin.int<2>} : (!riscv.reg<>, !snitch_stream.stride_pattern_type) -> !stream.readable<!riscv.freg<ft0>>
+// CHECK-NEXT:  "snitch.ssr_set_dimension_source"(%A) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<1>} : (!riscv.reg<>) -> ()
 // CHECK-NEXT:  %a = riscv.get_float_register : () -> !riscv.freg<ft0>
 
-%2 = "snitch_stream.strided_read"(%B, %0) {"dm" = #int<1>, "rank" = #int<2>} : (!riscv.reg<>, !snitch_stream.stride_pattern_type) -> !stream.readable<!riscv.freg<ft1>>
-// CHECK-NEXT:  "snitch.ssr_set_dimension_source"(%B) {"dm" = #int<1>, "dimension" = #int<1>} : (!riscv.reg<>) -> ()
+%2 = "snitch_stream.strided_read"(%B, %0) {"dm" = #builtin.int<1>, "rank" = #builtin.int<2>} : (!riscv.reg<>, !snitch_stream.stride_pattern_type) -> !stream.readable<!riscv.freg<ft1>>
+// CHECK-NEXT:  "snitch.ssr_set_dimension_source"(%B) {"dm" = #builtin.int<1>, "dimension" = #builtin.int<1>} : (!riscv.reg<>) -> ()
 // CHECK-NEXT:  %b = riscv.get_float_register : () -> !riscv.freg<ft1>
 
-%3 = "snitch_stream.strided_write"(%C, %0) {"dm" = #int<2>, "rank" = #int<2>} : (!riscv.reg<>, !snitch_stream.stride_pattern_type) -> !stream.writable<!riscv.freg<ft2>>
-// CHECK-NEXT:  "snitch.ssr_set_dimension_destination"(%C) {"dm" = #int<2>, "dimension" = #int<1>} : (!riscv.reg<>) -> ()
+%3 = "snitch_stream.strided_write"(%C, %0) {"dm" = #builtin.int<2>, "rank" = #builtin.int<2>} : (!riscv.reg<>, !snitch_stream.stride_pattern_type) -> !stream.writable<!riscv.freg<ft2>>
+// CHECK-NEXT:  "snitch.ssr_set_dimension_destination"(%C) {"dm" = #builtin.int<2>, "dimension" = #builtin.int<1>} : (!riscv.reg<>) -> ()
 
 
 %4 = riscv.li 6 : () -> !riscv.reg<>