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adding raymond golang handlebars implementation
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@willie68
willie68 committed Aug 11, 2022
1 parent acc3166 commit e12b55c
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2 changes: 2 additions & 0 deletions .gitignore
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wcupl/test/wcupl/
77 changes: 77 additions & 0 deletions WCPLD Examples/6502/W6502SBC.wpld
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header:
Name W6502SBC_16 ;
PartNo 01 ;
Date 05.08.2022 ;
Revision 01 ;
Designer wkla ;
Company nn ;
Assembly None ;
Location ;
Device G22V10 ;

pld:
/* *************** INPUT PINS *********************/
PIN 1 = PHI2;
PIN 2 = A15;
PIN 3 = A14;
PIN 4 = A13;
PIN 5 = A12;
PIN 6 = A11;
PIN 7 = A10;
PIN 8 = A9;
PIN 9 = A8;
//PIN 10 = nn;
PIN 11 = RW;
//PIN 13 = nn;

/* *************** OUTPUT PINS *********************/
PIN 23 = CSRAM;
PIN 22 = CSHIROM;
PIN 21 = CSEXTROM;
PIN 20 = CSIO;
PIN 19 = CSIO0;
PIN 18 = CSIO1;
PIN 17 = CSIO2;
PIN 16 = CSIO3;
PIN 15 = MWR; // /WR only for RAM
PIN 14 = MRD; // goes to all /OE of ROM and RAM

FIELD Addr = [A15..A8];

CSRAM = ! (Addr:[0000..7FFF]); // 32KB
CSIO = ! (Addr:[B000..BFFF]); // 4KB
CSIO0 = ! (Addr:[B000..B0FF]);
CSIO1 = ! (Addr:[B100..B1FF]);
CSIO2 = ! (Addr:[B200..B2FF]);
CSIO3 = ! (Addr:[B300..B3FF]);
CSEXTROM = ! (Addr:[8000..AFFF]); // 12KB
CSROM = ! (Addr:[C000..FFFF]); // 16KB

MWR = ! (PHI2 & !RW);
MRD = ! (PHI2 & RW);

simulator:
ORDER: A15, A14, A13, A12, A11, A10, A9, A8, RW, PHI2, CSRAM, CSIO, CSIO0, CSIO1, CSIO2, CSIO3, CSEXTROM, CSHIROM, MWR, MRD;

VECTORS:
/* RAM */
0 X X X X X X X 0 0 L H H H H H H H H H
0 X X X X X X X 0 1 L H H H H H H H L H
/* IO */
1 0 1 1 0 0 0 0 X X H L L H H H H H X X
1 0 1 1 0 0 0 1 X X H L H L H H H H X X
1 0 1 1 0 0 1 0 X X H L H H L H H H X X
1 0 1 1 0 0 1 1 X X H L H H H L H H X X
1 0 1 1 0 1 X X X X H L H H H H H H X X
1 0 1 1 1 X X X X X H L H H H H H H X X

/* 8000-AFFF external Rom */
1 0 0 0 X X X X X X H H H H H H L H X X
1 0 0 1 X X X X X X H H H H H H L H X X
1 0 1 0 X X X X X X H H H H H H L H X X

/* ROM */
1 1 X X X X X X 1 0 H H H H H H H L H H
1 1 X X X X X X 1 1 H H H H H H H L H L
1 1 X X X X X X 0 0 H H H H H H H L H H
1 1 X X X X X X 0 1 H H H H H H H L L H
63 changes: 63 additions & 0 deletions WCPLD Examples/6502/W6502SBC_C64.wpld
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header:
Name W6502SBC_ADR_C64 ;
PartNo 01 ;
Date 20.07.2022 ;
Revision 01 ;
Designer wkla ;
Company nn ;
Assembly None ;
Location ;
Device G16V8AS ;

pld:
/* *************** INPUT PINS *********************/
PIN 1 = A12;
PIN 2 = A13;
PIN 3 = A14;
PIN 4 = A15;
PIN 5 = ALORAM;
PIN 6 = AHIRAM;
PIN 7 = ALOROM;
PIN 8 = AHIROM;
PIN 9 = PHI2;
PIN 11 = NOLOROM;

/* *************** OUTPUT PINS *********************/
PIN 12 = CSRAM;
PIN 13 = CSHIROM;
PIN 14 = CSLOROM;
PIN 15 = CSIO;
PIN 16 = LORAM;
PIN 17 = LOROM;
PIN 18 = HIRAM;
PIN 19 = HIROM;


CSRAM = (A15 & !A14 & !A13 & !ALORAM) # (A15 & !A14 & A13 & NOLOROM) # (A15 & A14 & !A13 & !A12 & !AHIRAM) # (A15 & A14 & !A13 & A12) # (A15 & A14 & A13) # !PHI2;
CSHIROM = !(A15 & A14 & A13 & AHIROM);
CSLOROM = !(A15 & !A14 & A13 & ALOROM & NOLOROM);
CSIO= !(A15 & A14 & !A13 & A12);
LORAM= !(A15 & !A14 & !A13 & !ALORAM);
LOROM= !(A15 & !A14 & A13 & !ALOROM & NOLOROM);
HIRAM= !(A15 & A14 & !A13 & !A12 & !AHIRAM);
HIROM= !(A15 & A14 & A13 & !AHIROM);

simulator:
ORDER: A15, A14, A13, A12, ALORAM, AHIRAM, ALOROM, AHIROM, NOLOROM, PHI2, CSRAM, CSHIROM, CSLOROM, CSIO, LORAM, LOROM, HIRAM, HIROM;

VECTORS:
0 X X X X X X X X 0 H H H H H H H H
0 X X X X X X X X 1 L H H H H H H H
1 0 0 X 1 X X X X 0 H H H H H H H H
1 0 0 X 1 X X X X 1 L H H H H H H H
1 0 0 X 0 X X X X X H H H H L H H H
1 0 1 X X X 1 X 1 X H H L H H H H H
1 0 1 X X X 0 X 1 X H H H H H L H H
1 0 1 X X X X X 0 0 H H H H H H H H
1 0 1 X X X X X 0 1 L H H H H H H H
1 1 0 0 X 1 X X X 0 H H H H H H H H
1 1 0 0 X 1 X X X 1 L H H H H H H H
1 1 0 0 X 0 X X X X H H H H H H L H
1 1 0 1 X X X X X X H H H L H H H H
1 1 1 X X X X 1 X X H L H H H H H H
1 1 1 X X X X 0 X X H H H H H H H L
72 changes: 72 additions & 0 deletions WCPLD Examples/6502/adr_simple.wpld
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header:
Name adr_simple ;
PartNo 01 ;
Date 24.07.2022 ;
Revision 03 ;
Designer wkla ;
Company nn ;
Assembly None ;
Location ;
Device G16V8 ;

pld:
/* *************** INPUT PINS *********************/
PIN [1..8] = [A15..A8];
PIN 9 = PHI2;

/* *************** OUTPUT PINS *********************/
PIN 12 = CSRAM;
PIN 13 = CSHIROM;
PIN 14 = CSEXTROM;
PIN 15 = IOPORT;
PIN 16 = CSIO3PORT;
PIN 17 = CSIO2PORT;
PIN 18 = ACIAPORT;
PIN 19 = VIAPORT;
/* *************** LOGIC *********************/

FIELD Addr = [A15..A8];
CSRAM_EQU = Addr:[0000..7FFF]; // 32KB

/* IO */
IOPORT = ! (Addr:[B000..BFFF]); // 4KB
VIAPORT = ! (Addr:[B000..B0FF]);
ACIAPORT = ! (Addr:[B100..B1FF]);
CSIO2PORT = ! (Addr:[B200..B2FF]);
CSIO3PORT = ! (Addr:[B300..B3FF]);

/* 12KB of external ROM */
CSEXTROM = ! (Addr:[8000..AFFF]); // 12KB
/* 8kb of ROM */
CSHIROM = ! (Addr:[C000..FFFF]); // 16KB

/* RAM */
CSRAM = !CSRAM_EQU # !PHI2;

simulator:
ORDER: A15, A14, A13, A12, A11, A10, A9, A8, PHI2, CSEXTROM, CSRAM, CSHIROM, IOPORT, VIAPORT, ACIAPORT, CSIO2PORT, CSIO3PORT;

VECTORS:
/* internal RAM */
0 X X X X X X X 0 H H H H H H H H
0 X X X X X X X 1 H L H H H H H H

/* 8000-AFFF external Rom */
1 0 0 0 X X X X X L H H H H H H H
1 0 0 1 X X X X X L H H H H H H H
1 0 1 0 X X X X X L H H H H H H H

/* IO */
/* CSIO0 */
1 0 1 1 0 0 0 0 X H H H L L H H H
/* CSIO1 */
1 0 1 1 0 0 0 1 X H H H L H L H H
/* CSIO2 */
1 0 1 1 0 0 1 0 X H H H L H H L H
/* CSIO3 */
1 0 1 1 0 0 1 1 X H H H L H H H L
/* nicht direkt benutzt */
1 0 1 1 0 1 X X X H H H L H H H H
1 0 1 1 1 X X X X H H H L H H H H
/* ROM */
1 1 X X X X X X X H H L H H H H H
79 changes: 79 additions & 0 deletions WCPLD Examples/6502/adr_simple_v2.wpld
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header:
Name adr_simple ;
PartNo 01 ;
Date 24.07.2022 ;
Revision 03 ;
Designer wkla ;
Company nn ;
Assembly None ;
Location ;
Device G16V8 ;

pld:
/* *************** INPUT PINS *********************/
PIN [1..8] = [A15..A8];
PIN 9 = PHI2;
PIN 11 = RW;

/* *************** OUTPUT PINS *********************/
PIN 12 = CSRAM;
PIN 13 = CSHIROM;
PIN 14 = CSEXTROM;
PIN 15 = CSIO;
PIN 16 = MWR;
PIN 17 = CSIO2;
PIN 18 = CSIO1;
PIN 19 = CSIO0;
/* *************** LOGIC *********************/

FIELD Addr = [A15..A8];

/* RAM 32kb */
CSRAM = ! (Addr:[0000..7FFF]);

/* IO 4kb */
CSIO = ! (Addr:[B000..BFFF]);
CSIO0 = ! (Addr:[B000..B0FF]);
CSIO1 = ! (Addr:[B100..B1FF]);
CSIO2 = ! (Addr:[B200..B2FF]);

/* 12kb of external ROM */
CSEXTROM = ! (Addr:[8000..AFFF]);

/* 16kb of ROM */
CSHIROM = ! (Addr:[C000..FFFF]);

MWR = ! (PHI2 & !RW);

simulator:
ORDER: A15, A14, A13, A12, A11, A10, A9, A8, RW, PHI2, CSRAM, MWR, CSIO, CSIO0, CSIO1, CSIO2, CSEXTROM, CSHIROM;

VECTORS:
/* testing /RD /WR */
X X X X X X X X 0 0 X H X X X X X X
X X X X X X X X 0 1 X L X X X X X X
X X X X X X X X 1 0 X H X X X X X X
X X X X X X X X 1 1 X H X X X X X X

/* internal RAM */
0 X X X X X X X X X L X H H H H H H

/* 8000-AFFF external Rom */
1 0 0 0 X X X X X X H X H H H H L H
1 0 0 1 X X X X X X H X H H H H L H
1 0 1 0 X X X X X X H X H H H H L H

/* IO */
/* CSIO0 */
1 0 1 1 0 0 0 0 X X H X L L H H H H
/* CSIO1 */
1 0 1 1 0 0 0 1 X X H X L H L H H H
/* CSIO2 */
1 0 1 1 0 0 1 0 X X H X L H H L H H

/* nicht direkt benutzt */
1 0 1 1 0 1 X X X X H X L H H H H H
1 0 1 1 1 X X X X X H X L H H H H H

/* ROM */
1 1 X X X X X X X X H X H H H H H L
93 changes: 93 additions & 0 deletions WCPLD Examples/7-seg decoder/7segDecoder - Kopie.wpld
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header:
Name 7segDecoder ;
PartNo 00 ;
Date 8/6/2020 ;
Revision 02 ;
Designer Peter Murray ;
Company N/A ;
Assembly None ;
Location Right here ;
Device g16v8ms ;

/*
Hex to 7-segment LED display converter
Common Cathode Variant

+----\/----+
CLK | 1 20 | Vcc
I0 | 2 19 | Segment A
I1 | 3 18 | Segment B
I2 | 4 17 | Segment C
I3 | 5 16 | Segment D
N/C | 6 15 | Segment E
N/C | 7 14 | Segment F
N/C | 8 13 | Segment G
N/C | 9 12 | N/C
GND | 10 11 | /OE
+----------+

This is designed for the Atmel ATF16V8B (Digikey: ATF16V8B-15PU-ND )

*/
pld:
/* *************** INPUT PINS *********************/
PIN 1 = CLK;
PIN 2 = I0;
PIN 3 = I1;
PIN 4 = I2;
PIN 5 = I3;
/* PIN 11 = !ENABLE; */

/* *************** OUTPUT PINS ******************** */
PIN 19 = !A;
PIN 18 = !B;
PIN 17 = !C;
PIN 16 = !D;
PIN 15 = !E;
PIN 14 = !F;
PIN 13 = !G;

/* [A,B,C,D,E,F,G].oe = ENABLE; */

FIELD INPUT = [I0,I1,I2,I3]; /* Defines input array */
FIELD OUTPUT = [A.d,B.d,C.d,D.d,E.d,F.d,G.d]; /* Defines output array */
TABLE INPUT => OUTPUT
{
'b'0000 => 'b'0000001;
'b'0001 => 'b'1001111;
'b'0010 => 'b'0010010;
'b'0011 => 'b'0000110;
'b'0100 => 'b'1001100;
'b'0101 => 'b'0100100;
'b'0110 => 'b'0100000;
'b'0111 => 'b'0001111;
'b'1000 => 'b'0000000;
'b'1001 => 'b'0001100;
'b'1010 => 'b'0001000;
'b'1011 => 'b'1100000;
'b'1100 => 'b'0110001;
'b'1101 => 'b'1000010;
'b'1110 => 'b'0110000;
'b'1111 => 'b'0111000;
}
/*
{
'b'0000 => 'b'1111110;
'b'0001 => 'b'0110000;
'b'0010 => 'b'1101101;
'b'0011 => 'b'1111001;
'b'0100 => 'b'0110011;
'b'0101 => 'b'1011011;
'b'0110 => 'b'1011111;
'b'0111 => 'b'1110000;
'b'1000 => 'b'1111111;
'b'1001 => 'b'1110011;
'b'1010 => 'b'1110111;
'b'1011 => 'b'0011111;
'b'1100 => 'b'1001110;
'b'1101 => 'b'0111101;
'b'1110 => 'b'1001111;
'b'1111 => 'b'1000111;
}
*/
simulator:
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