SAP-1 8 bit-CPU described in verilog and synthesized onto a PYNQ-Z2 FPGA development board connected to a 4 digit 7 segment display for output.
Demo shows the cpu running a program that counts up to 255 and counts back down to 0. Push button 0 on FPGA dev board is used to reset the program.
IMG_2691.mov
Repo includes full vivado project file inside "/8bitCPU" folder. I've also included the individual verilog files for use with other FPGA dev boards.