Updated schema :

longer but smaller ^^' (possibility to solder arduino and mcp module directly without header connectors)
ulysse31 · Jun 15, 2019 · 41925e3 · 41925e3
1 parent 9919267
commit 41925e3
Show file tree

Hide file tree

Showing 7 changed files with 137 additions and 145 deletions.
diff --git a/Hardware/USB_Powered/CID_Faker.bin b/Hardware/USB_Powered/CID_Faker.bin
diff --git a/Hardware/USB_Powered/CID_Faker.dsn b/Hardware/USB_Powered/CID_Faker.dsn
@@ -3,7 +3,7 @@
     (string_quote ")
     (space_in_quoted_tokens on)
     (host_cad "KiCad's Pcbnew")
-    (host_version "4.0.7")
+    (host_version "(5.1.2-1)-1")
   )
   (resolution um 10)
   (unit um)
@@ -21,8 +21,8 @@
       )
     )
     (boundary
-      (path pcb 0  143891 -90043  125349 -90043  125349 -124079  143891 -124079
-            143891 -90043  143891 -90043)
+      (path pcb 0  143891 -124079  125349 -124079  125349 -90043  143891 -90043
+            143891 -124079)
     )
     (via "Via[0-1]_600:400_um")
     (rule
@@ -33,29 +33,30 @@
     )
   )
   (placement
-    (component Socket_Strips:Socket_Strip_Straight_1x07_Pitch2.54mm
-      (place J2 127000 -122301 back 90 (PN CAN))
+    (component Connector_PinSocket_2.54mm:PinSocket_1x07_P2.54mm_Vertical
+      (place J1 127000 -91440 back 90 (PN CAN1))
     )
     (component promicro:ProMicro
-      (place U1 134620 -105283 front 90 (PN ProMicro))
+      (place U1 134620 -107950 front 90 (PN ProMicro))
     )
   )
   (library
-    (image Socket_Strips:Socket_Strip_Straight_1x07_Pitch2.54mm
-      (outline (path signal 100  -1270 1270  -1270 -16510))
-      (outline (path signal 100  -1270 -16510  1270 -16510))
-      (outline (path signal 100  1270 -16510  1270 1270))
-      (outline (path signal 100  1270 1270  -1270 1270))
+    (image Connector_PinSocket_2.54mm:PinSocket_1x07_P2.54mm_Vertical
+      (outline (path signal 100  -1270 1270  635 1270))
+      (outline (path signal 100  635 1270  1270 635))
+      (outline (path signal 100  1270 635  1270 -16510))
+      (outline (path signal 100  1270 -16510  -1270 -16510))
+      (outline (path signal 100  -1270 -16510  -1270 1270))
+      (outline (path signal 120  -1330 -1270  1330 -1270))
       (outline (path signal 120  -1330 -1270  -1330 -16570))
       (outline (path signal 120  -1330 -16570  1330 -16570))
-      (outline (path signal 120  1330 -16570  1330 -1270))
-      (outline (path signal 120  1330 -1270  -1330 -1270))
-      (outline (path signal 120  -1330 0  -1330 1330))
-      (outline (path signal 120  -1330 1330  0 1330))
-      (outline (path signal 50  -1800 1800  -1800 -17050))
-      (outline (path signal 50  -1800 -17050  1800 -17050))
-      (outline (path signal 50  1800 -17050  1800 1800))
-      (outline (path signal 50  1800 1800  -1800 1800))
+      (outline (path signal 120  1330 -1270  1330 -16570))
+      (outline (path signal 120  1330 1330  1330 0))
+      (outline (path signal 120  0 1330  1330 1330))
+      (outline (path signal 50  -1800 1800  1750 1800))
+      (outline (path signal 50  1750 1800  1750 -17000))
+      (outline (path signal 50  1750 -17000  -1800 -17000))
+      (outline (path signal 50  -1800 -17000  -1800 1800))
       (pin Rect[A]Pad_1700x1700_um 1 0 0)
       (pin Oval[A]Pad_1700x1700_um 2 0 -2540)
       (pin Oval[A]Pad_1700x1700_um 3 0 -5080)
@@ -134,31 +135,31 @@
   )
   (network
     (net GND
-      (pins J2-6 U1-3 U1-4 U1-23)
+      (pins J1-6 U1-3 U1-4)
     )
     (net INT
-      (pins J2-1 U1-5)
+      (pins J1-1 U1-5)
     )
     (net SCK
-      (pins J2-2 U1-16)
+      (pins J1-2 U1-16)
     )
     (net MOSI
-      (pins J2-3 U1-14)
+      (pins J1-3 U1-14)
     )
     (net MISO
-      (pins J2-4 U1-15)
+      (pins J1-4 U1-15)
     )
     (net CS
-      (pins J2-5 U1-8)
+      (pins J1-5 U1-8)
     )
     (net VCC
-      (pins J2-7 U1-21)
+      (pins J1-7 U1-21)
     )
     (class kicad_default "" CS GND INT MISO MOSI "Net-(U1-Pad1)" "Net-(U1-Pad10)"
       "Net-(U1-Pad11)" "Net-(U1-Pad12)" "Net-(U1-Pad13)" "Net-(U1-Pad17)"
       "Net-(U1-Pad18)" "Net-(U1-Pad19)" "Net-(U1-Pad2)" "Net-(U1-Pad20)" "Net-(U1-Pad22)"
-      "Net-(U1-Pad24)" "Net-(U1-Pad6)" "Net-(U1-Pad7)" "Net-(U1-Pad9)" RAW
-      SCK VCC VIN
+      "Net-(U1-Pad23)" "Net-(U1-Pad24)" "Net-(U1-Pad6)" "Net-(U1-Pad7)" "Net-(U1-Pad9)"
+      SCK VCC
       (circuit
         (use_via Via[0-1]_600:400_um)
       )

diff --git a/Hardware/USB_Powered/CID_Faker.kicad_pcb b/Hardware/USB_Powered/CID_Faker.kicad_pcb
@@ -3,7 +3,7 @@
   (general
     (thickness 1.6)
     (drawings 5)
-    (tracks 30)
+    (tracks 29)
     (zones 0)
     (modules 2)
     (nets 8)
@@ -115,7 +115,7 @@
   )
 
   (module Connector_PinSocket_2.54mm:PinSocket_1x07_P2.54mm_Vertical (layer B.Cu) (tedit 5A19A433) (tstamp 5CFFE7A6)
-    (at 127 121.92 270)
+    (at 127 91.44 270)
     (descr "Through hole straight socket strip, 1x07, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
     (tags "Through hole socket strip THT 1x07 2.54mm single row")
     (path /5CFEC3BA)
@@ -165,7 +165,7 @@
   )
 
   (module promicro:ProMicro (layer F.Cu) (tedit 5A06A962) (tstamp 5CFFE7D2)
-    (at 134.62 105.41 90)
+    (at 134.62 107.95 90)
     (descr "Pro Micro footprint")
     (tags "promicro ProMicro")
     (path /5CFEB39A)
@@ -221,48 +221,46 @@
     (pad 21 thru_hole circle (at -6.35 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask F.SilkS)
       (net 7 VCC))
     (pad 22 thru_hole circle (at -8.89 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
-    (pad 23 thru_hole circle (at -11.43 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask F.SilkS)
-      (net 1 GND))
+    (pad 23 thru_hole circle (at -11.43 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
     (pad 24 thru_hole circle (at -13.97 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask F.SilkS))
   )
 
-  (gr_text "Designed by\nUlysse31 a.k.a Nix\n[email protected]\n" (at 135.89 102.87 90) (layer B.Cu)
+  (gr_text "Designed by\nUlysse31 a.k.a Nix\n[email protected]\n" (at 133.35 111.76 90) (layer B.Cu) (tstamp 5D0524F1)
     (effects (font (size 1.5 1.5) (thickness 0.3)) (justify mirror))
   )
   (gr_line (start 143.891 90.043) (end 143.891 124.079) (angle 90) (layer Edge.Cuts) (width 0.15))
   (gr_line (start 125.349 90.043) (end 143.891 90.043) (angle 90) (layer Edge.Cuts) (width 0.15))
   (gr_line (start 125.349 124.079) (end 125.349 90.043) (angle 90) (layer Edge.Cuts) (width 0.15))
   (gr_line (start 143.891 124.079) (end 125.349 124.079) (angle 90) (layer Edge.Cuts) (width 0.15))
 
-  (segment (start 139.7 120.57) (end 139.7 120.3918) (width 0.5) (layer B.Cu) (net 1))
-  (segment (start 139.7 120.3918) (end 136.1482 116.84) (width 0.5) (layer B.Cu) (net 1))
-  (segment (start 136.1482 116.84) (end 127 116.84) (width 0.5) (layer B.Cu) (net 1))
-  (segment (start 142.24 114.3) (end 139.7 116.84) (width 0.5) (layer F.Cu) (net 1))
-  (segment (start 139.7 116.84) (end 139.7 121.92) (width 0.5) (layer F.Cu) (net 1))
-  (segment (start 142.24 111.76) (end 142.24 114.3) (width 0.5) (layer F.Cu) (net 1))
-  (segment (start 139.7 121.92) (end 139.7 120.57) (width 0.5) (layer B.Cu) (net 1))
-  (segment (start 137.8372 119.5902) (end 129.3298 119.5902) (width 0.5) (layer B.Cu) (net 2))
-  (segment (start 129.3298 119.5902) (end 127 121.92) (width 0.5) (layer B.Cu) (net 2))
-  (segment (start 142.24 109.22) (end 137.8372 113.6228) (width 0.5) (layer F.Cu) (net 2))
-  (segment (start 137.8372 113.6228) (end 137.8372 119.5902) (width 0.5) (layer F.Cu) (net 2))
-  (via (at 137.8372 119.5902) (size 0.6) (layers F.Cu B.Cu) (net 2))
-  (segment (start 127 99.06) (end 129.4467 101.5067) (width 0.5) (layer F.Cu) (net 3))
-  (segment (start 129.4467 101.5067) (end 129.4467 120.4767) (width 0.5) (layer F.Cu) (net 3))
-  (segment (start 129.4467 120.4767) (end 129.54 120.57) (width 0.5) (layer F.Cu) (net 3))
-  (segment (start 129.54 121.92) (end 129.54 120.57) (width 0.5) (layer F.Cu) (net 3))
-  (segment (start 132.08 120.57) (end 130.1504 118.6404) (width 0.5) (layer F.Cu) (net 4))
-  (segment (start 130.1504 118.6404) (end 130.1504 100.9245) (width 0.5) (layer F.Cu) (net 4))
-  (segment (start 127 93.98) (end 130.1504 97.1304) (width 0.5) (layer B.Cu) (net 4))
-  (segment (start 130.1504 97.1304) (end 130.1504 100.9245) (width 0.5) (layer B.Cu) (net 4))
-  (segment (start 132.08 121.92) (end 132.08 120.57) (width 0.5) (layer F.Cu) (net 4))
-  (via (at 130.1504 100.9245) (size 0.6) (layers F.Cu B.Cu) (net 4))
-  (segment (start 127 96.52) (end 134.62 104.14) (width 0.5) (layer F.Cu) (net 5))
-  (segment (start 134.62 104.14) (end 134.62 121.92) (width 0.5) (layer F.Cu) (net 5))
-  (segment (start 142.24 101.6) (end 137.0869 106.7531) (width 0.5) (layer F.Cu) (net 6))
-  (segment (start 137.0869 106.7531) (end 137.0869 120.4969) (width 0.5) (layer F.Cu) (net 6))
-  (segment (start 137.0869 120.4969) (end 137.16 120.57) (width 0.5) (layer F.Cu) (net 6))
-  (segment (start 137.16 121.92) (end 137.16 120.57) (width 0.5) (layer F.Cu) (net 6))
-  (segment (start 127 111.76) (end 132.08 111.76) (width 0.5) (layer B.Cu) (net 7))
-  (segment (start 132.08 111.76) (end 142.24 121.92) (width 0.5) (layer B.Cu) (net 7))
+  (segment (start 139.7 91.44) (end 139.7 92.79) (width 0.5) (layer F.Cu) (net 1))
+  (segment (start 140.7495 101.9195) (end 140.7495 93.8395) (width 0.5) (layer F.Cu) (net 1))
+  (segment (start 140.7495 93.8395) (end 139.7 92.79) (width 0.5) (layer F.Cu) (net 1))
+  (segment (start 142.24 114.3) (end 140.7495 112.8095) (width 0.5) (layer B.Cu) (net 1))
+  (segment (start 140.7495 112.8095) (end 140.7495 101.9195) (width 0.5) (layer B.Cu) (net 1))
+  (segment (start 142.24 114.3) (end 142.24 116.84) (width 0.5) (layer F.Cu) (net 1))
+  (via (at 140.7495 101.9195) (size 0.6) (layers F.Cu B.Cu) (net 1))
+  (segment (start 127 91.44) (end 127.2429 91.44) (width 0.5) (layer B.Cu) (net 2))
+  (segment (start 127.2429 91.44) (end 129.5683 93.7654) (width 0.5) (layer B.Cu) (net 2))
+  (segment (start 142.24 111.76) (end 129.5683 99.0883) (width 0.5) (layer F.Cu) (net 2))
+  (segment (start 129.5683 99.0883) (end 129.5683 93.7654) (width 0.5) (layer F.Cu) (net 2))
+  (via (at 129.5683 93.7654) (size 0.6) (layers F.Cu B.Cu) (net 2))
+  (segment (start 129.54 92.79) (end 129.4826 92.79) (width 0.5) (layer F.Cu) (net 3))
+  (segment (start 129.4826 92.79) (end 128.818 93.4546) (width 0.5) (layer F.Cu) (net 3))
+  (segment (start 128.818 93.4546) (end 128.818 99.782) (width 0.5) (layer F.Cu) (net 3))
+  (segment (start 128.818 99.782) (end 127 101.6) (width 0.5) (layer F.Cu) (net 3))
+  (segment (start 129.54 91.44) (end 129.54 92.79) (width 0.5) (layer F.Cu) (net 3))
+  (segment (start 132.08 91.44) (end 132.08 92.79) (width 0.5) (layer B.Cu) (net 4))
+  (segment (start 127 96.52) (end 128.35 96.52) (width 0.5) (layer B.Cu) (net 4))
+  (segment (start 128.35 96.52) (end 132.08 92.79) (width 0.5) (layer B.Cu) (net 4))
+  (segment (start 134.62 91.44) (end 134.62 92.79) (width 0.5) (layer B.Cu) (net 5))
+  (segment (start 127 99.06) (end 133.27 92.79) (width 0.5) (layer B.Cu) (net 5))
+  (segment (start 133.27 92.79) (end 134.62 92.79) (width 0.5) (layer B.Cu) (net 5))
+  (segment (start 137.16 91.44) (end 137.16 99.3911) (width 0.5) (layer F.Cu) (net 6))
+  (segment (start 137.16 99.3911) (end 141.9089 104.14) (width 0.5) (layer F.Cu) (net 6))
+  (segment (start 141.9089 104.14) (end 142.24 104.14) (width 0.5) (layer F.Cu) (net 6))
+  (segment (start 127 114.3) (end 134.511 106.789) (width 0.5) (layer B.Cu) (net 7))
+  (segment (start 134.511 106.789) (end 134.511 99.169) (width 0.5) (layer B.Cu) (net 7))
+  (segment (start 134.511 99.169) (end 142.24 91.44) (width 0.5) (layer B.Cu) (net 7))
 
 )
diff --git a/Hardware/USB_Powered/CID_Faker.net b/Hardware/USB_Powered/CID_Faker.net
@@ -1,7 +1,7 @@
 (export (version D)
   (design
     (source /Users/nix/Documents/PlatformIO/Projects/CID_Faker/Hardware/USB_Powered/CID_Faker.sch)
-    (date "2019 June 12, Wednesday 19:22:30")
+    (date "2019 June 15, Saturday 19:09:22")
     (tool "Eeschema (5.1.2-1)-1")
     (sheet (number 1) (name /) (tstamps /)
       (title_block
@@ -110,26 +110,27 @@
       (node (ref U1) (pin 13)))
     (net (code 15) (name "Net-(U1-Pad24)")
       (node (ref U1) (pin 24)))
-    (net (code 16) (name INT)
-      (node (ref J1) (pin 1))
-      (node (ref U1) (pin 5)))
-    (net (code 17) (name SCK)
+    (net (code 16) (name "Net-(U1-Pad23)")
+      (node (ref U1) (pin 23)))
+    (net (code 17) (name INT)
+      (node (ref U1) (pin 5))
+      (node (ref J1) (pin 1)))
+    (net (code 18) (name SCK)
       (node (ref U1) (pin 16))
       (node (ref J1) (pin 2)))
-    (net (code 18) (name MOSI)
-      (node (ref J1) (pin 3))
-      (node (ref U1) (pin 14)))
-    (net (code 19) (name MISO)
-      (node (ref J1) (pin 4))
-      (node (ref U1) (pin 15)))
-    (net (code 20) (name CS)
+    (net (code 19) (name MOSI)
+      (node (ref U1) (pin 14))
+      (node (ref J1) (pin 3)))
+    (net (code 20) (name MISO)
+      (node (ref U1) (pin 15))
+      (node (ref J1) (pin 4)))
+    (net (code 21) (name CS)
       (node (ref U1) (pin 8))
       (node (ref J1) (pin 5)))
-    (net (code 21) (name GND)
-      (node (ref U1) (pin 23))
-      (node (ref U1) (pin 4))
+    (net (code 22) (name GND)
       (node (ref U1) (pin 3))
-      (node (ref J1) (pin 6)))
-    (net (code 22) (name VCC)
+      (node (ref J1) (pin 6))
+      (node (ref U1) (pin 4)))
+    (net (code 23) (name VCC)
       (node (ref U1) (pin 21))
       (node (ref J1) (pin 7)))))
diff --git a/Hardware/USB_Powered/CID_Faker.rules b/Hardware/USB_Powered/CID_Faker.rules
@@ -11,7 +11,7 @@
     (via_costs 50)
     (plane_via_costs 5)
     (start_ripup_costs 100)
-    (start_pass_no 106)
+    (start_pass_no 124)
     (layer_rule F.Cu
       (active on)
       (preferred_direction vertical)

diff --git a/Hardware/USB_Powered/CID_Faker.sch b/Hardware/USB_Powered/CID_Faker.sch
@@ -1,5 +1,4 @@
 EESchema Schematic File Version 4
-LIBS:CID_Faker-cache
 EELAYER 29 0
 EELAYER END
 $Descr A4 11693 8268
@@ -26,8 +25,6 @@ Text GLabel 3300 1300 1    60   Input ~ 0
 VCC
 Text GLabel 4300 2400 2    60   Input ~ 0
 VCC
-Text GLabel 4300 2200 2    60   Input ~ 0
-GND
 Text GLabel 3900 1300 1    60   Input ~ 0
 INT
 Text GLabel 3800 1300 1    60   Input ~ 0
@@ -83,4 +80,5 @@ Text GLabel 2900 2400 0    50   Input ~ 0
 GND
 Text GLabel 2900 2300 0    50   Input ~ 0
 GND
+NoConn ~ 4300 2200
 $EndSCHEMATC