EDA algorithm engineer
- Shanghai
-
11:07
(UTC -12:00) - https://cocorong.com
- in/jingrong-lin-02888817b
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verilog-to-routing/vtr-verilog-to-routing
verilog-to-routing/vtr-verilog-to-routing PublicVerilog to Routing -- Open Source CAD Flow for FPGA Research
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