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assets
assets
 
 
tools
tools
 
 
README.md
README.md
 
 
clkdiv.v
clkdiv.v
 
 
clkgate.v
clkgate.v
 
 
counters.v
counters.v
 
 
data_matrix.v
data_matrix.v
 
 
ddc1.v
ddc1.v
 
 
ddr_io.v
ddr_io.v
 
 
debounce.v
debounce.v
 
 
dither.v
dither.v
 
 
dsmod1.v
dsmod1.v
 
 
dsmod2.v
dsmod2.v
 
 
fifo.v
fifo.v
 
 
i2s_rx.v
i2s_rx.v
 
 
ice40hx8k-evb.pcf
ice40hx8k-evb.pcf
 
 
integrator.v
integrator.v
 
 
johnson.v
johnson.v
 
 
keyboard.v
keyboard.v
 
 
playground.pcf
playground.pcf
 
 
primitives.v
primitives.v
 
 
pwm.v
pwm.v
 
 
pwm_pr.v
pwm_pr.v
 
 
rgb_to_gray.v
rgb_to_gray.v
 
 
rom.v
rom.v
 
 
round.v
round.v
 
 
sequencer.v
sequencer.v
 
 
sim.v
sim.v
 
 
spi_slave.v
spi_slave.v
 
 
stack.v
stack.v
 
 
tb_clkdiv.v
tb_clkdiv.v
 
 
tb_clkdiv_2_3.v
tb_clkdiv_2_3.v
 
 
tb_clkdiv_prog.v
tb_clkdiv_prog.v
 
 
tb_clkdiv_prog_l.v
tb_clkdiv_prog_l.v
 
 
tb_clkgate.v
tb_clkgate.v
 
 
tb_ctr_pr.v
tb_ctr_pr.v
 
 
tb_dsmod.v
tb_dsmod.v
 
 
tb_fifo.v
tb_fifo.v
 
 
tb_fifo_8.v
tb_fifo_8.v
 
 
tb_fifo_cke.v
tb_fifo_cke.v
 
 
tb_fifo_multi.v
tb_fifo_multi.v
 
 
tb_i2s_rx.v
tb_i2s_rx.v
 
 
tb_integrator.v
tb_integrator.v
 
 
tb_johnson.v
tb_johnson.v
 
 
tb_pwm.v
tb_pwm.v
 
 
tb_pwm_pr.v
tb_pwm_pr.v
 
 
tb_rgb_to_gray.v
tb_rgb_to_gray.v
 
 
tb_rom.v
tb_rom.v
 
 
tb_round.v
tb_round.v
 
 
tb_sequencer.v
tb_sequencer.v
 
 
tb_stack.v
tb_stack.v
 
 
tb_uart_matrix.v
tb_uart_matrix.v
 
 
tb_uart_rx.v
tb_uart_rx.v
 
 
tb_uart_rx_ddr.v
tb_uart_rx_ddr.v
 
 
tb_uart_rx_no.v
tb_uart_rx_no.v
 
 
tb_uart_rx_no_dr.v
tb_uart_rx_no_dr.v
 
 
tb_uart_rx_vo.v
tb_uart_rx_vo.v
 
 
tb_uart_rx_vo_dr.v
tb_uart_rx_vo_dr.v
 
 
uart_matrix.v
uart_matrix.v
 
 
uart_rtscts.v
uart_rtscts.v
 
 
uart_rx.v
uart_rx.v
 
 
uart_tx.v
uart_tx.v
 
 
vga_tx.v
vga_tx.v
 
 
video_test.v
video_test.v
 
 

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ice40_lib

This is a Verilog library made specifically for Lattice iCE40HX/LX devices.

It contains random bits and bytes that I needed or wanted.

Most of the modules are generic Verilog files that will work with any FPGAs, but some use specific iCE40 primitives for certain reasons. All design choices were made with iCE40 family in mind (such as utilization of 4kb RAM cells).

Files prefixed with "tb_" are testbenches and run in Icarus Verilog, like so:

iverilog tb_xxx.v && ./a.out

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