remove asm feature

The `asm!()` macro was stabilized in
rust-lang/rust#91728. This removes the feature
and imports it through `core::arch` instead.

arch/cortex-m/src/lib.rs

@@ -2,10 +2,11 @@
 
 #![crate_name = "cortexm"]
 #![crate_type = "rlib"]
-#![feature(asm, asm_sym)]
+#![feature(asm_sym)]
 #![feature(naked_functions)]
 #![no_std]
 
+use core::arch::asm;
 use core::fmt::Write;
 
 pub mod mpu;

arch/cortex-m/src/scb.rs

@@ -2,6 +2,8 @@
 //!
 //! <http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/CIHFDJCA.html>
 
+use core::arch::asm;
+
 use kernel::utilities::registers::interfaces::{ReadWriteable, Readable, Writeable};
 use kernel::utilities::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite};
 use kernel::utilities::StaticRef;

arch/cortex-m/src/support.rs

@@ -1,3 +1,4 @@
+use core::arch::asm;
 use core::ops::FnOnce;
 
 #[cfg(all(target_arch = "arm", target_os = "none"))]

arch/cortex-m0/src/lib.rs

@@ -2,7 +2,7 @@
 
 #![crate_name = "cortexm0"]
 #![crate_type = "rlib"]
-#![feature(asm, asm_sym, naked_functions)]
+#![feature(asm_sym, naked_functions)]
 #![no_std]
 
 // Re-export the base generic cortex-m functions here as they are
@@ -13,6 +13,8 @@ pub use cortexm::nvic;
 pub use cortexm::print_cortexm_state as print_cortexm0_state;
 pub use cortexm::syscall;
 
+use core::arch::asm;
+
 extern "C" {
     // _estack is not really a function, but it makes the types work
     // You should never actually invoke it!!

arch/cortex-m0p/src/lib.rs

@@ -2,7 +2,6 @@
 
 #![crate_name = "cortexm0p"]
 #![crate_type = "rlib"]
-#![feature(asm)]
 #![feature(naked_functions)]
 #![no_std]
 
@@ -26,6 +25,8 @@ pub use cortexm0::generic_isr;
 pub use cortexm0::hard_fault_handler;
 pub use cortexm0::systick_handler;
 
+use core::arch::asm;
+
 // Mock implementation for tests on Travis-CI.
 #[cfg(not(any(target_arch = "arm", target_os = "none")))]
 pub unsafe extern "C" fn switch_to_user(

arch/rv32i/src/lib.rs

@@ -2,9 +2,10 @@
 
 #![crate_name = "rv32i"]
 #![crate_type = "rlib"]
-#![feature(asm, asm_sym, const_fn_trait_bound, naked_functions)]
+#![feature(asm_sym, const_fn_trait_bound, naked_functions)]
 #![no_std]
 
+use core::arch::asm;
 use core::fmt::Write;
 
 use kernel::utilities::registers::interfaces::{Readable, Writeable};

arch/rv32i/src/support.rs

@@ -1,6 +1,7 @@
 //! Core low-level operations.
 
 use crate::csr::{mstatus::mstatus, CSR};
+use core::arch::asm;
 use core::ops::FnOnce;
 
 #[cfg(all(target_arch = "riscv32", target_os = "none"))]

arch/rv32i/src/syscall.rs

@@ -1,5 +1,6 @@
 //! Kernel-userland system call interface for RISC-V architecture.
 
+use core::arch::asm;
 use core::convert::TryInto;
 use core::fmt::Write;
 use core::mem::size_of;

boards/nano_rp2040_connect/src/main.rs

@@ -7,7 +7,9 @@
 // https://github.com/rust-lang/rust/issues/62184.
 #![cfg_attr(not(doc), no_main)]
 #![deny(missing_docs)]
-#![feature(asm, naked_functions)]
+#![feature(naked_functions)]
+
+use core::arch::asm;
 
 use capsules::virtual_alarm::VirtualMuxAlarm;
 use components::gpio::GpioComponent;

boards/pico_explorer_base/src/main.rs

@@ -7,7 +7,9 @@
 // https://github.com/rust-lang/rust/issues/62184.
 #![cfg_attr(not(doc), no_main)]
 #![deny(missing_docs)]
-#![feature(asm, naked_functions)]
+#![feature(naked_functions)]
+
+use core::arch::asm;
 
 use kernel::dynamic_deferred_call::{DynamicDeferredCall, DynamicDeferredCallClientState};
 

boards/raspberry_pi_pico/src/main.rs

@@ -7,7 +7,9 @@
 // https://github.com/rust-lang/rust/issues/62184.
 #![cfg_attr(not(doc), no_main)]
 #![deny(missing_docs)]
-#![feature(asm, naked_functions)]
+#![feature(naked_functions)]
+
+use core::arch::asm;
 
 use capsules::i2c_master::I2CMasterDriver;
 use capsules::virtual_alarm::VirtualMuxAlarm;

chips/apollo3/src/lib.rs

@@ -2,7 +2,7 @@
 
 #![crate_name = "apollo3"]
 #![crate_type = "rlib"]
-#![feature(asm, const_fn_trait_bound)]
+#![feature(const_fn_trait_bound)]
 #![no_std]
 
 // Peripherals
@@ -18,6 +18,8 @@ pub mod pwrctrl;
 pub mod stimer;
 pub mod uart;
 
+use core::arch::asm;
+
 use cortexm4::{
     generic_isr, hard_fault_handler, initialize_ram_jump_to_main, scb, svc_handler,
     systick_handler, unhandled_interrupt,

chips/arty_e21_chip/src/chip.rs

@@ -1,3 +1,4 @@
+use core::arch::asm;
 use core::fmt::Write;
 use kernel;
 use kernel::debug;

chips/arty_e21_chip/src/lib.rs

@@ -1,6 +1,5 @@
 //! Drivers and chip support for the E21 soft core.
 
-#![feature(asm)]
 #![no_std]
 #![crate_name = "arty_e21_chip"]
 #![crate_type = "rlib"]

chips/earlgrey/src/chip.rs

@@ -1,5 +1,6 @@
 //! High-level setup and interrupt mapping for the chip.
 
+use core::arch::asm;
 use core::fmt::Write;
 use kernel;
 use kernel::dynamic_deferred_call::DynamicDeferredCall;

chips/earlgrey/src/lib.rs

@@ -1,6 +1,6 @@
 //! Drivers and chip support for EarlGrey.
 
-#![feature(asm, const_fn_trait_bound, naked_functions)]
+#![feature(const_fn_trait_bound, naked_functions)]
 #![no_std]
 #![crate_name = "earlgrey"]
 #![crate_type = "rlib"]

chips/esp32-c3/src/chip.rs

@@ -1,5 +1,6 @@
 //! High-level setup and interrupt mapping for the chip.
 
+use core::arch::asm;
 use core::fmt::Write;
 
 use kernel;

chips/esp32-c3/src/lib.rs

@@ -1,6 +1,6 @@
 //! Drivers and chip support for ESP32-C3.
 
-#![feature(const_fn_trait_bound, naked_functions, asm)]
+#![feature(const_fn_trait_bound, naked_functions)]
 #![no_std]
 #![crate_name = "esp32_c3"]
 #![crate_type = "rlib"]

chips/litex_vexriscv/src/interrupt_controller.rs

@@ -107,6 +107,7 @@ mod vexriscv_irq_raw {
     #[cfg(all(target_arch = "riscv32", target_os = "none"))]
     pub unsafe fn irq_getmask() -> usize {
         let mask: usize;
+        use core::arch::asm;
         asm!("csrr {mask}, {csr}", mask = out(reg) mask, csr = const CSR_IRQ_MASK);
         mask
     }
@@ -116,6 +117,7 @@ mod vexriscv_irq_raw {
 
     #[cfg(all(target_arch = "riscv32", target_os = "none"))]
     pub unsafe fn irq_setmask(mask: usize) {
+        use core::arch::asm;
         asm!("csrw {csr}, {mask}", csr = const CSR_IRQ_MASK, mask = in(reg) mask);
     }
 
@@ -127,6 +129,7 @@ mod vexriscv_irq_raw {
     #[cfg(all(target_arch = "riscv32", target_os = "none"))]
     pub unsafe fn irq_pending() -> usize {
         let pending: usize;
+        use core::arch::asm;
         asm!("csrr {pending}, {csr}", pending = out(reg) pending, csr = const CSR_IRQ_PENDING);
         pending
     }

chips/litex_vexriscv/src/lib.rs

@@ -1,6 +1,6 @@
 //! LiteX SoCs based around a VexRiscv CPU
 
-#![feature(asm, asm_const, const_fn_trait_bound)]
+#![feature(asm_const, const_fn_trait_bound)]
 #![no_std]
 #![crate_name = "litex_vexriscv"]
 #![crate_type = "rlib"]

chips/msp432/src/lib.rs

@@ -1,6 +1,6 @@
 #![crate_name = "msp432"]
 #![crate_type = "rlib"]
-#![feature(asm, const_fn_trait_bound)]
+#![feature(const_fn_trait_bound)]
 #![no_std]
 
 use cortexm4::{

chips/rp2040/src/clocks.rs

@@ -1,3 +1,4 @@
+use core::arch::asm;
 use core::cell::Cell;
 use kernel::utilities::registers::interfaces::{ReadWriteable, Readable, Writeable};
 use kernel::utilities::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite};

chips/rp2040/src/lib.rs

@@ -1,4 +1,4 @@
-#![feature(const_fn_trait_bound, asm)]
+#![feature(const_fn_trait_bound)]
 #![no_std]
 
 pub mod adc;

chips/stm32f4xx/src/fsmc.rs

@@ -1,4 +1,5 @@
 use crate::rcc;
+use core::arch::asm;
 use core::cell::Cell;
 use kernel::deferred_call::DeferredCall;
 use kernel::hil::bus8080::{Bus8080, BusWidth, Client};

chips/stm32f4xx/src/lib.rs

@@ -5,7 +5,6 @@
 #![crate_name = "stm32f4xx"]
 #![crate_type = "rlib"]
 #![feature(const_fn_trait_bound)]
-#![feature(asm)]
 #![no_std]
 
 pub mod chip;

chips/swervolf-eh1/src/lib.rs

@@ -1,6 +1,6 @@
 //! Drivers and chip support for SweRVolf.
 
-#![feature(asm, const_fn_trait_bound, naked_functions)]
+#![feature(const_fn_trait_bound, naked_functions)]
 #![no_std]
 #![crate_name = "swervolf_eh1"]
 #![crate_type = "rlib"]

libraries/riscv-csr/src/csr.rs

@@ -1,5 +1,6 @@
 //! `ReadWriteRiscvCsr` type for RISC-V CSRs.
 
+use core::arch::asm;
 use core::marker::PhantomData;
 
 use tock_registers::fields::Field;

libraries/riscv-csr/src/lib.rs

@@ -2,7 +2,7 @@
 //!
 //! Uses the Tock Register Interface to control RISC-V CSRs.
 
-#![feature(asm, asm_const)]
+#![feature(asm_const)]
 #![feature(const_fn_trait_bound)]
 #![no_std]