Merge #2959

2959: Update Nightly to Feb 2022 r=hudson-ayers a=bradjc ### Pull Request Overview The headline here being: `asm!()` is stabilized! (As of rust-lang/rust#91728.) Most changes are to remove the asm feature and add `use core::arch:asm`. ### Testing Strategy travis ### TODO or Help Wanted Resolved: ~~Can someone look at https://github.com/tock/tock/compare/update-nightly-feb-2022?expand=1#diff-494cb9c3b94f58f1ab43cca69f63906088f87a97726d9260665f8529f605f2c9L259? I had to remove some clobbers to remove an error. I think that is ok (https://stackoverflow.com/questions/41380345/how-to-use-hir8-r12-register-in-cortex-m0) but I'm not sure.~~ ### Documentation Updated - [x] Updated the relevant files in `/docs`, or no updates are required. ### Formatting - [x] Ran `make prepush`. Co-authored-by: Brad Campbell <[email protected]>
tock · Mar 4, 2022 · af4c24f · af4c24f
2 parents aeb62a5 + dab6ffa
commit af4c24f
Show file tree

Hide file tree

Showing 32 changed files with 65 additions and 22 deletions.
diff --git a/.vscode/settings.json b/.vscode/settings.json
@@ -1,4 +1,4 @@
 {
     "editor.formatOnSave": true,
-    "rust-client.channel": "nightly-2021-12-04",
+    "rust-client.channel": "nightly-2022-02-23",
 }
diff --git a/arch/cortex-m/src/lib.rs b/arch/cortex-m/src/lib.rs
@@ -2,7 +2,7 @@
 
 #![crate_name = "cortexm"]
 #![crate_type = "rlib"]
-#![feature(asm, asm_sym)]
+#![feature(asm_sym)]
 #![feature(naked_functions)]
 #![no_std]
 
@@ -40,6 +40,7 @@ extern "C" {
 ))]
 #[naked]
 pub unsafe extern "C" fn systick_handler_arm_v7m() {
+    use core::arch::asm;
     asm!(
         "
     // Set thread mode to privileged to switch back to kernel mode.
@@ -70,6 +71,7 @@ pub unsafe extern "C" fn systick_handler_arm_v7m() {
 ))]
 #[naked]
 pub unsafe extern "C" fn svc_handler_arm_v7m() {
+    use core::arch::asm;
     asm!(
         "
     // First check to see which direction we are going in. If the link register
@@ -132,6 +134,7 @@ pub unsafe extern "C" fn svc_handler_arm_v7m() {
 ))]
 #[naked]
 pub unsafe extern "C" fn generic_isr_arm_v7m() {
+    use core::arch::asm;
     asm!(
         "
     // Set thread mode to privileged to ensure we are executing as the kernel.
@@ -209,6 +212,7 @@ pub unsafe extern "C" fn generic_isr_arm_v7m() {
 
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 pub unsafe extern "C" fn unhandled_interrupt() {
+    use core::arch::asm;
     let mut interrupt_number: u32;
 
     // IPSR[8:0] holds the currently active interrupt
@@ -232,6 +236,7 @@ pub unsafe extern "C" fn unhandled_interrupt() {
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 #[naked]
 pub unsafe extern "C" fn initialize_ram_jump_to_main() {
+    use core::arch::asm;
     asm!(
         "
     // Start by initializing .bss memory. The Tock linker script defines
@@ -298,6 +303,7 @@ pub unsafe extern "C" fn switch_to_user_arm_v7m(
     mut user_stack: *const usize,
     process_regs: &mut [usize; 8],
 ) -> *const usize {
+    use core::arch::asm;
     asm!(
     "
     // Rust `asm!()` macro (as of May 2021) will not let us mark r6, r7 and r9
@@ -514,6 +520,7 @@ unsafe extern "C" fn hard_fault_handler_arm_v7m_continued(
     kernel_stack: u32,
     stack_overflow: u32,
 ) {
+    use core::arch::asm;
     if kernel_stack != 0 {
         if stack_overflow != 0 {
             // Panic to show the correct error.
@@ -570,6 +577,7 @@ unsafe extern "C" fn hard_fault_handler_arm_v7m_continued(
 ))]
 #[naked]
 pub unsafe extern "C" fn hard_fault_handler_arm_v7m() {
+    use core::arch::asm;
     // First need to determine if this a kernel fault or a userspace fault, and store
     // the unmodified stack pointer. Place these values in registers, then call
     // a non-naked function, to allow for use of rust code alongside inline asm.

diff --git a/arch/cortex-m/src/scb.rs b/arch/cortex-m/src/scb.rs
@@ -298,6 +298,7 @@ pub unsafe fn set_vector_table_offset(offset: *const ()) {
 /// Disable the FPU
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 pub unsafe fn disable_fpca() {
+    use core::arch::asm;
     SCB.cpacr
         .modify(CoprocessorAccessControl::CP10::CLEAR + CoprocessorAccessControl::CP11::CLEAR);
 

diff --git a/arch/cortex-m/src/support.rs b/arch/cortex-m/src/support.rs
@@ -4,6 +4,7 @@ use core::ops::FnOnce;
 #[inline(always)]
 /// NOP instruction
 pub fn nop() {
+    use core::arch::asm;
     unsafe {
         asm!("nop", options(nomem, nostack, preserves_flags));
     }
@@ -13,6 +14,7 @@ pub fn nop() {
 #[inline(always)]
 /// WFI instruction
 pub unsafe fn wfi() {
+    use core::arch::asm;
     asm!("wfi", options(nomem, preserves_flags));
 }
 
@@ -21,6 +23,7 @@ pub unsafe fn atomic<F, R>(f: F) -> R
 where
     F: FnOnce() -> R,
 {
+    use core::arch::asm;
     // Set PRIMASK
     asm!("cpsid i", options(nomem, nostack));
 

diff --git a/arch/cortex-m0/src/lib.rs b/arch/cortex-m0/src/lib.rs
@@ -2,7 +2,7 @@
 
 #![crate_name = "cortexm0"]
 #![crate_type = "rlib"]
-#![feature(asm, asm_sym, naked_functions)]
+#![feature(asm_sym, naked_functions)]
 #![no_std]
 
 // Re-export the base generic cortex-m functions here as they are
@@ -35,6 +35,7 @@ pub unsafe extern "C" fn generic_isr() {
 #[naked]
 /// All ISRs are caught by this handler which disables the NVIC and switches to the kernel.
 pub unsafe extern "C" fn generic_isr() {
+    use core::arch::asm;
     asm!(
         "
     /* Skip saving process state if not coming from user-space */
@@ -130,6 +131,7 @@ pub unsafe extern "C" fn systick_handler() {
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 #[naked]
 pub unsafe extern "C" fn systick_handler() {
+    use core::arch::asm;
     asm!(
         "
     // Set thread mode to privileged to switch back to kernel mode.
@@ -161,6 +163,7 @@ pub unsafe extern "C" fn svc_handler() {
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 #[naked]
 pub unsafe extern "C" fn svc_handler() {
+    use core::arch::asm;
     asm!(
         "
   ldr r0, 200f // EXC_RETURN_MSP
@@ -201,6 +204,7 @@ pub unsafe extern "C" fn switch_to_user(
     mut user_stack: *const u8,
     process_regs: &mut [usize; 8],
 ) -> *mut u8 {
+    use core::arch::asm;
     asm!("
     // Rust `asm!()` macro (as of May 2021) will not let us mark r6, r7 and r9
     // as clobbers. r6 and r9 is used internally by LLVM, and r7 is used for
@@ -323,6 +327,7 @@ pub unsafe extern "C" fn hard_fault_handler() {
 /// can mix `asm!()` and Rust. We separate this logic to not have to write the
 /// entire fault handler entirely in assembly.
 unsafe extern "C" fn hard_fault_handler_continued(faulting_stack: *mut u32, kernel_stack: u32) {
+    use core::arch::asm;
     if kernel_stack != 0 {
         kernel_hardfault(faulting_stack);
     } else {
@@ -385,6 +390,7 @@ unsafe extern "C" fn hard_fault_handler_continued(faulting_stack: *mut u32, kern
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 #[naked]
 pub unsafe extern "C" fn hard_fault_handler() {
+    use core::arch::asm;
     // If `kernel_stack` is non-zero, then hard-fault occurred in
     // kernel, otherwise the hard-fault occurred in user.
     asm!("

diff --git a/arch/cortex-m0p/src/lib.rs b/arch/cortex-m0p/src/lib.rs
@@ -2,7 +2,6 @@
 
 #![crate_name = "cortexm0p"]
 #![crate_type = "rlib"]
-#![feature(asm)]
 #![feature(naked_functions)]
 #![no_std]
 
@@ -44,6 +43,7 @@ pub unsafe extern "C" fn svc_handler() {
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 #[naked]
 pub unsafe extern "C" fn svc_handler() {
+    use core::arch::asm;
     asm!(
         "
   ldr r0, 100f // EXC_RETURN_MSP

diff --git a/arch/rv32i/src/lib.rs b/arch/rv32i/src/lib.rs
@@ -2,7 +2,7 @@
 
 #![crate_name = "rv32i"]
 #![crate_type = "rlib"]
-#![feature(asm, asm_sym, const_fn_trait_bound, naked_functions)]
+#![feature(asm_sym, const_fn_trait_bound, naked_functions)]
 #![no_std]
 
 use core::fmt::Write;
@@ -55,6 +55,7 @@ extern "C" {
 #[export_name = "_start"]
 #[naked]
 pub extern "C" fn _start() {
+    use core::arch::asm;
     unsafe {
         asm! ("
             // Set the global pointer register using the variable defined in the
@@ -191,6 +192,7 @@ pub extern "C" fn _start_trap() {
 #[export_name = "_start_trap"]
 #[naked]
 pub extern "C" fn _start_trap() {
+    use core::arch::asm;
     unsafe {
         asm!(
             "
@@ -438,6 +440,7 @@ pub extern "C" fn _start_trap() {
 /// https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/XKkYacERM04/m/CdpOcqtRAgAJ
 #[cfg(all(target_arch = "riscv32", target_os = "none"))]
 pub unsafe fn semihost_command(command: usize, arg0: usize, arg1: usize) -> usize {
+    use core::arch::asm;
     let res;
     asm!(
     "

diff --git a/arch/rv32i/src/support.rs b/arch/rv32i/src/support.rs
@@ -7,6 +7,7 @@ use core::ops::FnOnce;
 #[inline(always)]
 /// NOP instruction
 pub fn nop() {
+    use core::arch::asm;
     unsafe {
         asm!("nop", options(nomem, nostack, preserves_flags));
     }
@@ -16,6 +17,7 @@ pub fn nop() {
 #[inline(always)]
 /// WFI instruction
 pub unsafe fn wfi() {
+    use core::arch::asm;
     asm!("wfi", options(nomem, nostack));
 }
 

diff --git a/arch/rv32i/src/syscall.rs b/arch/rv32i/src/syscall.rs
@@ -230,6 +230,7 @@ impl kernel::syscall::UserspaceKernelBoundary for SysCall {
         _app_brk: *const u8,
         state: &mut Riscv32iStoredState,
     ) -> (ContextSwitchReason, Option<*const u8>) {
+        use core::arch::asm;
         // We need to ensure that the compiler does not reorder
         // kernel memory writes to after the userspace context switch
         // to ensure we provide a consistent memory view of

diff --git a/boards/nano_rp2040_connect/src/main.rs b/boards/nano_rp2040_connect/src/main.rs
@@ -7,7 +7,9 @@
 // https://github.com/rust-lang/rust/issues/62184.
 #![cfg_attr(not(doc), no_main)]
 #![deny(missing_docs)]
-#![feature(asm, naked_functions)]
+#![feature(naked_functions)]
+
+use core::arch::asm;
 
 use capsules::virtual_alarm::VirtualMuxAlarm;
 use components::gpio::GpioComponent;

diff --git a/boards/pico_explorer_base/src/main.rs b/boards/pico_explorer_base/src/main.rs
@@ -7,7 +7,9 @@
 // https://github.com/rust-lang/rust/issues/62184.
 #![cfg_attr(not(doc), no_main)]
 #![deny(missing_docs)]
-#![feature(asm, naked_functions)]
+#![feature(naked_functions)]
+
+use core::arch::asm;
 
 use kernel::dynamic_deferred_call::{DynamicDeferredCall, DynamicDeferredCallClientState};
 

diff --git a/boards/raspberry_pi_pico/src/main.rs b/boards/raspberry_pi_pico/src/main.rs
@@ -7,7 +7,9 @@
 // https://github.com/rust-lang/rust/issues/62184.
 #![cfg_attr(not(doc), no_main)]
 #![deny(missing_docs)]
-#![feature(asm, naked_functions)]
+#![feature(naked_functions)]
+
+use core::arch::asm;
 
 use capsules::i2c_master::I2CMasterDriver;
 use capsules::virtual_alarm::VirtualMuxAlarm;

diff --git a/chips/apollo3/src/lib.rs b/chips/apollo3/src/lib.rs
@@ -2,7 +2,7 @@
 
 #![crate_name = "apollo3"]
 #![crate_type = "rlib"]
-#![feature(asm, const_fn_trait_bound)]
+#![feature(const_fn_trait_bound)]
 #![no_std]
 
 // Peripherals
@@ -76,6 +76,7 @@ pub static PATCH: [unsafe extern "C" fn(); 16] = [unhandled_interrupt; 16];
 
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 pub unsafe fn init() {
+    use core::arch::asm;
     let cache_ctrl = crate::cachectrl::CacheCtrl::new();
     cache_ctrl.enable_cache();
 

diff --git a/chips/arty_e21_chip/src/chip.rs b/chips/arty_e21_chip/src/chip.rs
@@ -109,6 +109,7 @@ impl<'a, I: InterruptService<()> + 'a> ArtyExx<'a, I> {
     /// valid for platforms with a CLIC.
     #[cfg(all(target_arch = "riscv32", target_os = "none"))]
     pub unsafe fn configure_trap_handler(&self) {
+        use core::arch::asm;
         asm!(
             "
             // The csrw instruction writes a Control and Status Register (CSR)

diff --git a/chips/arty_e21_chip/src/lib.rs b/chips/arty_e21_chip/src/lib.rs
@@ -1,6 +1,5 @@
 //! Drivers and chip support for the E21 soft core.
 
-#![feature(asm)]
 #![no_std]
 #![crate_name = "arty_e21_chip"]
 #![crate_type = "rlib"]

diff --git a/chips/earlgrey/src/chip.rs b/chips/earlgrey/src/chip.rs
@@ -401,6 +401,7 @@ pub extern "C" fn _start_trap_vectored() {
 #[export_name = "_start_trap_vectored"]
 #[naked]
 pub extern "C" fn _start_trap_vectored() -> ! {
+    use core::arch::asm;
     unsafe {
         // According to the Ibex user manual:
         // [NMI] has interrupt ID 31, i.e., it has the highest priority of all

diff --git a/chips/earlgrey/src/lib.rs b/chips/earlgrey/src/lib.rs
@@ -1,6 +1,6 @@
 //! Drivers and chip support for EarlGrey.
 
-#![feature(asm, const_fn_trait_bound, naked_functions)]
+#![feature(const_fn_trait_bound, naked_functions)]
 #![no_std]
 #![crate_name = "earlgrey"]
 #![crate_type = "rlib"]

diff --git a/chips/esp32-c3/src/chip.rs b/chips/esp32-c3/src/chip.rs
@@ -299,6 +299,7 @@ pub extern "C" fn _start_trap_vectored() {
 #[export_name = "_start_trap_vectored"]
 #[naked]
 pub extern "C" fn _start_trap_vectored() -> ! {
+    use core::arch::asm;
     unsafe {
         // Below are 32 (non-compressed) jumps to cover the entire possible
         // range of vectored traps.

diff --git a/chips/esp32-c3/src/lib.rs b/chips/esp32-c3/src/lib.rs
@@ -1,6 +1,6 @@
 //! Drivers and chip support for ESP32-C3.
 
-#![feature(const_fn_trait_bound, naked_functions, asm)]
+#![feature(const_fn_trait_bound, naked_functions)]
 #![no_std]
 #![crate_name = "esp32_c3"]
 #![crate_type = "rlib"]

diff --git a/chips/litex_vexriscv/src/interrupt_controller.rs b/chips/litex_vexriscv/src/interrupt_controller.rs
@@ -107,6 +107,7 @@ mod vexriscv_irq_raw {
     #[cfg(all(target_arch = "riscv32", target_os = "none"))]
     pub unsafe fn irq_getmask() -> usize {
         let mask: usize;
+        use core::arch::asm;
         asm!("csrr {mask}, {csr}", mask = out(reg) mask, csr = const CSR_IRQ_MASK);
         mask
     }
@@ -116,6 +117,7 @@ mod vexriscv_irq_raw {
 
     #[cfg(all(target_arch = "riscv32", target_os = "none"))]
     pub unsafe fn irq_setmask(mask: usize) {
+        use core::arch::asm;
         asm!("csrw {csr}, {mask}", csr = const CSR_IRQ_MASK, mask = in(reg) mask);
     }
 
@@ -127,6 +129,7 @@ mod vexriscv_irq_raw {
     #[cfg(all(target_arch = "riscv32", target_os = "none"))]
     pub unsafe fn irq_pending() -> usize {
         let pending: usize;
+        use core::arch::asm;
         asm!("csrr {pending}, {csr}", pending = out(reg) pending, csr = const CSR_IRQ_PENDING);
         pending
     }

diff --git a/chips/litex_vexriscv/src/lib.rs b/chips/litex_vexriscv/src/lib.rs
@@ -1,6 +1,6 @@
 //! LiteX SoCs based around a VexRiscv CPU
 
-#![feature(asm, asm_const, const_fn_trait_bound)]
+#![feature(asm_const, const_fn_trait_bound)]
 #![no_std]
 #![crate_name = "litex_vexriscv"]
 #![crate_type = "rlib"]

diff --git a/chips/msp432/src/lib.rs b/chips/msp432/src/lib.rs
@@ -1,6 +1,6 @@
 #![crate_name = "msp432"]
 #![crate_type = "rlib"]
-#![feature(asm, const_fn_trait_bound)]
+#![feature(const_fn_trait_bound)]
 #![no_std]
 
 use cortexm4::{

diff --git a/chips/rp2040/src/clocks.rs b/chips/rp2040/src/clocks.rs
@@ -1044,6 +1044,7 @@ impl Clocks {
             let _delay_cyc: u32 = self.get_frequency(Clock::System) / self.get_frequency(clock) + 1;
             #[cfg(target_arch = "arm")]
             unsafe {
+                use core::arch::asm;
                 asm! (
                     "1:",
                     "subs {0}, #1",

diff --git a/chips/rp2040/src/lib.rs b/chips/rp2040/src/lib.rs
@@ -1,4 +1,4 @@
-#![feature(const_fn_trait_bound, asm)]
+#![feature(const_fn_trait_bound)]
 #![no_std]
 
 pub mod adc;